Mediaspace scheduled maintenance: Aug 25, 2026 07:00 - 12:00 AM. During this time, videos will be temporarily unavailable. Check status updates.

Concept

Puce d'accélération de réseaux de neurones

Publications associées (30)

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Equinox: Training (for Free) on a Custom Inference Accelerator

Babak Falsafi, Martin Jaggi, Mario Paulo Drumond Lages De Oliveira, Ahmet Caner Yüzügüler, Arash Pourhabibi Zarandi, Louis Coulon

DNN inference accelerators executing online services exhibit low average loads because of service demand variability, leading to poor resource utilization. Unfortunately, reclaiming idle inference cycles is difficult as other workloads can not execute on a ...

ACM2021

Architecture Exploration and Optimization of Heterogeneous Many-Core Compute and Memory Architectures with Architectural Extensions

Yasir Mahmood Qureshi

The expeditious proliferation of Internet connectivity and the growing adoption of digital products have transformed various spheres of our everyday lives. This increased digitization of society has led to the emergence of new applications, which are deplo ...

EPFL2021

Synthesis of Flexible Accelerators for Early Adoption of Ring-LWE Post-quantum Cryptography

Francesco Regazzoni, Subhadeep Banik

The advent of the quantum computer makes current public-key infrastructure insecure. Cryptography community is addressing this problem by designing, efficiently implementing, and evaluating novel public-key algorithms capable of withstanding quantum comput ...

ASSOC COMPUTING MACHINERY2020

ColTraIn: Co-located DNN training and inference

Mario Paulo Drumond Lages De Oliveira

Deep neural network inference accelerators are deployed at scale to accommodate online services, but face low average load because of service demand variability, leading to poor resource utilization. Unfortunately, reclaiming inference idle cycles is diffi ...

EPFL2020

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches) a ...

ASSOC COMPUTING MACHINERY2020

Quantum ESPRESSO toward the exascale

Nicola Marzari, Iurii Timrov

Quantum ESPRESSO is an open-source distribution of computer codes for quantum-mechanical materials modeling, based on density-functional theory, pseudopotentials, and plane waves, and renowned for its performance on a wide range of hardware architectures, ...

AMER INST PHYSICS2020

Lupulus: A Flexible Hardware Accelerator For Neural Networks

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Robert Giterman, Andreas Toftegaard Kristensen

Neural networks have become indispensable for a wide range of applications, but they suffer from high computational- and memory-requirements, requiring optimizations from the algorithmic description of the network to the hardware implementation. Moreover, ...

IEEE2020

Blade: An in-Cache Computing Architecture for Edge Devices

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, William Andrew Simon, Yasir Mahmood Qureshi

Area and power constrained edge devices are increasingly utilized to perform compute intensive workloads, necessitating increasingly area and power efficient accelerators. In this context, in-SRAM computing performs hundreds of parallel operations on spati ...

2020

Combining Dynamic & Static Scheduling in High-level Synthesis

Paolo Ienne, Lana Josipovic

ASSOC COMPUTING MACHINERY2020