Publications associées à Algorithme de Tomasulo

Imprecise Store Exceptions

Babak Falsafi, Mathias Josef Payer, Siddharth Gupta, Yunho Oh, Yuanlong Li, Abhishek Bhattacharjee, Qingxuan Kang

Precise exceptions are a cornerstone of modern computing as they provide the abstraction of sequential instruction execution to programmers while accommodating microarchitectural optimizations. However, increasing compute capabilities in deep memory hierar ...

ACM2023

Time scales of dynamic stall development on a vertical-axis wind turbine blade

Karen Ann J Mulleners, Sébastien Le Fouest, Daniel Marie Fernex

Vertical-axis wind turbines are excellent candidates to diversify wind energy technology, but their aerodynamic complexity limits industrial deployment. To improve the efficiency and lifespan of vertical-axis wind turbines, we desire data-driven models and ...

2023

All you need is time to generalise the Goman-Khrabrov dynamic stall model

Karen Ann J Mulleners, Fatma Ayancik Cinoglu

Dynamic stall on airfoils negatively impacts their aerodynamic performance and can lead to structural damage. Accurate prediction and modelling of the dynamic stall loads are crucial for a more robust design of wings and blades that operate under unsteady ...

Cambridge University Press2022

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches) a ...

ASSOC COMPUTING MACHINERY2020

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Paolo Ienne, Mikhail Asiatici

FPGAs rely on massive datapath parallelism to accelerate applications even with a low clock frequency. However, applications such as sparse linear algebra and graph analytics have their throughput limited by irregular accesses to external memory for which ...

ASSOC COMPUTING MACHINERY2019

An Out-of-Order Load-Store Queue for Spatial Computing

Paolo Ienne, Philip Brisk, Lana Josipovic

The efficiency of spatial computing depends on the ability to achieve maximal parallelism. This necessitates memory interfaces that can correctly handle memory accesses that arrive in arbitrary order while still respecting data dependencies and ensuring ap ...

Assoc Computing Machinery2017

Everything You Always Wanted to Know about Multicore Graph Processing but Were Afraid to Ask

Willy Zwaenepoel, Baptiste Joseph Eustache Lepers, Jasmina Malicevic

Graph processing systems are used in a wide variety of fields, ranging from biology to social networks, and a large number of such systems have been described in the recent literature. We perform a systematic comparison of various techniques proposed to sp ...

USENIX Association2017

SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads

Anastasia Ailamaki, Pinar Tözün

Online transaction processing (OLTP) is at the core of many data center applications. OLTP workloads are known to have large instruction footprints that foil existing L1 instruction caches resulting in poor overall performance. Prefetching can reduce the i ...

2012

Speculative Linearizability

Rachid Guerraoui, Viktor Kuncak, Giuliano Losa

Linearizability is a key design methodology for reasoning about implementations of concurrent abstract data types in both shared memory and message passing systems. It provides the illusion that operations execute sequentially and fault-free, despite the a ...

Assoc Computing Machinery2012

Reducing OLTP Instruction Misses With Thread Migration

Anastasia Ailamaki, Pinar Tözün

During an instruction miss a processor is unable to fetch instructions. The more frequent instruction misses are the less able a modern processor is to find useful work to do and thus performance suffers. Online transaction processing (OLTP) suffers from h ...

2012

High-Performance RMA-Based Broadcast on the Intel SCC

André Schiper, Thomas Ropars, Omid Shahmirzadi, Darko Petrovic

Many-core chips with more than 1000 cores are expected by the end of the decade. To overcome scalability issues related to cache coherence at such a scale, one of the main research directions is to leverage the message-passing programming model. The Intel ...

2012