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Concept

X86

Publications associées (29)

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Rebooting Virtual Memory with Midgard

Siddharth Gupta

Virtual Memory (VM) is a critical programming abstraction that is widely used in various modern computing platforms. With the rise of datacenter computing and birth of planet-scale online services, the semantic and capacity requirements from memory have ev ...

EPFL2023

Hardware Implementation of Digital Signal Processing Algorithms for Programmable Epilepsy Control Systems

Keyvan Farhang Razi

Epilepsy is a common chronic neurological disorder that causes recurring seizures and affects more than 50 million people worldwide. Implantable medical devices (IMDs) are regarded as effective tools to cure patients who suffer from refractory epilepsy. Se ...

EPFL2023

A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication

David Atienza Alonso, Giovanni Ansaloni, Marco Antonio Rios, Grégoire Axel Eggermann

State-of-the-art Artificial Intelligence (AI) algorithms, such as graph neural networks and recommendation systems, require floating-point computation of very large matrix multiplications over sparse data. Their execution in resource-constrained scenarios, ...

New York2023

VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

David Atienza Alonso, Miguel Peon Quiros, Benoît Walter Denkinger

Edge-computing requires high-performance energy-efficient embedded systems. Fixed-function or custom accelerators, such as FFT or FIR filter engines, are very efficient at implementing a particular functionality for a given set of constraints. However, the ...

ASSOC COMPUTING MACHINERY2022

Faster Parallel Training of Word Embeddings

Martin Jaggi

Word embeddings have gained increasing popularity in the recent years due to the Word2vec library and its extension fastText that uses subword information. In this paper, we aim at improving the execution speed of fastText training on homogeneous multi- an ...

IEEE COMPUTER SOC2021

Synthesis of Flexible Accelerators for Early Adoption of Ring-LWE Post-quantum Cryptography

Francesco Regazzoni, Subhadeep Banik

The advent of the quantum computer makes current public-key infrastructure insecure. Cryptography community is addressing this problem by designing, efficiently implementing, and evaluating novel public-key algorithms capable of withstanding quantum comput ...

ASSOC COMPUTING MACHINERY2020

Micro-architectural Analysis of OLAP: Limitations and Opportunities

Anastasia Ailamaki, Utku Sirin

Understanding micro-architectural behavior is important for efficiently using hardware resources. Recent work has shown that in-memory online transaction processing (OLTP) systems severely underutilize their core micro-architecture resources [29]. Whereas, ...

ASSOC COMPUTING MACHINERY2020

Y QC-MDPC Decoders with Several Shades of Gray

Dusan Kostic

QC-MDPC code-based KEMs rely on decoders that have a small or even negligible Decoding Failure Rate (DFR). These decoders should be efficient and implementable in constant-time. One example for a QC-MDPC KEM is the Round-2 candidate of the NIST PQC standar ...

SPRINGER INTERNATIONAL PUBLISHING AG2020

Benchmarking JPEG XL image compression

Touradj Ebrahimi, Evgeniy Upenik

JPEG XL is a practical, royalty-free codec for scalable web distribution and efficient compression of high-quality photographs. It also includes previews, progressiveness, animation, transparency, high dynamic range, wide color gamut, and high bit depth. U ...

SPIE2020

Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs

Marco Mattavelli, Endri Bezati, Simone Casale Brunet, Anatoly Prihozhy

Large dataflow designs are a result of behavioral specification of modern complex digital systems and/or a result of unfolding and transforming looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resour ...

SPRINGER2020

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Yunho Oh

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp thr ...

ASSOC COMPUTING MACHINERY2019

SoK: Shining Light on Shadow Stacks

Mathias Josef Payer

Control-Flow Hijacking attacks are the dominant attack vector against C/C++ programs. Control-Flow Integrity (CFI) solutions mitigate these attacks on the forward edge, i.e., indirect calls through function pointers and virtual calls. Protecting the backwa ...

IEEE COMPUTER SOC2019

Hardware-conscious Query Processing in GPU-accelerated Analytical Engines

Anastasia Ailamaki, Periklis Chrysogelos, Panagiotis Sioulas

In order to improve their power efficiency and computational capacity, modern servers are adopting hardware accelerators, especially GPUs. Modern analytical DMBS engines have been highly optimized for multi-core multi-CPU query execution, but lack the nece ...

2019

Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing

Christian Enz, Vincent Frédéric Camus

The current trend for deep learning has come with an enormous computational need for billions of Multiply-Accumulate (MAC) operations per inference. Fortunately, reduced precision has demonstrated large benefits with low impact on accuracy, paving the way ...

2019

HetExchange: Encapsulating heterogeneous CPU-GPU parallelism in JIT compiled engines

Anastasia Ailamaki, Raja Appuswamy, Manolis Karpathiotakis, Periklis Chrysogelos

Modern server hardware is increasingly heterogeneous as hardware accelerators, such as GPUs, are used together with multicore CPUs to meet the computational demands of modern data analytics workloads. Unfortunately, query parallelization techniques used by ...

2019

Adaptive Cache Mode Selection for Queries over Raw Data

Anastasia Ailamaki, Tahir Azim

Caching the results of intermediate query results for future re-use is a common technique for improving the performance of analytics over raw data sources. An important design choice in this regard is whether to lazily cache only the offsets of satisfying ...

2018

Oblivious Dynamic Searchable Encryption on Distributed Cloud Systems

Fatma Betül Durak

Dynamic Searchable Symmetric Encryption (DSSE) allows search/update operations over encrypted data via an encrypted index. However, DSSE has been shown to be vulnerable to statistical inference attacks, which can extract a significant amount of information ...

SPRINGER INTERNATIONAL PUBLISHING AG2018

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines

Marco Mattavelli, Endri Bezati, Simone Casale Brunet, Anatoly Prihozhy

Large dataflow designs appear as a result of functional specification of modern complex digital systems and/ or a result of unfolding and behavioral transformation of looped and branched programs. Since deep-submicron silicon technology provides large amou ...

IEEE2018

Network-Compute Co-Design for Distributed In-Memory Computing

Alexandros Daglis

The booming popularity of online services is rapidly raising the demands for modern datacenters. In order to cope with data deluge, growing user bases, and tight quality of service constraints, service providers deploy massive datacenters with tens to hund ...

EPFL2018