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Concept

Exécution spéculative

Publications associées (30)

TSLAM: a tag-based object-centered monocular navigation system for augmented manual woodworking

Yves Weinand, Julien Gamerro, Andrea Settimi, Hong-Bin Yang

TimberSLAM (TSLAM) is an object-centered, tag-based visual self-localization and mapping (SLAM) system for monocular RGB cameras. It was specifically developed to support a robust and augmented reality pipeline for close-range, noisy, and cluttered fabrica ...

2024

LAQy: Efficient and Reusable Query Approximations via Lazy Sampling

Anastasia Ailamaki, Viktor Sanca, Periklis Chrysogelos

Modern analytical engines rely on Approximate Query Processing (AQP) to provide faster response times than the hardware allows for exact query answering. However, existing AQP methods impose steep performance penalties as workload unpredictability increase ...

2023

Improving K-means Clustering Using Speculation

Anastasia Ailamaki, Viktor Sanca, Eleni Zapridou, Stefan Igescu

K-means is one of the fundamental unsupervised data clustering and machine learning methods. It has been well studied over the years: parallelized, approximated, and optimized for different cases and applications. With increasingly higher parallelism leadi ...

2023

Rebooting Virtual Memory with Midgard

Siddharth Gupta

Virtual Memory (VM) is a critical programming abstraction that is widely used in various modern computing platforms. With the rise of datacenter computing and birth of planet-scale online services, the semantic and capacity requirements from memory have ev ...

EPFL2023

A lightweight learning-based decoding algorithm for intraneural vagus nerve activity classification in pigs

Silvestro Micera, Ivo Strauss, Leonardo Pollina

Objective. Bioelectronic medicine is an emerging field that aims at developing closed-loop neuromodulation protocols for the autonomic nervous system (ANS) to treat a wide range of disorders. When designing a closed-loop protocol for real time modulation o ...

IOP Publishing Ltd2022

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

Vishal Gupta

High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequen ...

ASSOC COMPUTING MACHINERY2022

Advancing the Adaptability of Compliant Robot Controllers for Exploration, Interaction, and Manipulation

Farshad Khadivar

As technology continues to evolve, robots are becoming an intrinsic part of our lives. While robots surpass human capabilities in precision and speed, they are far from matching humans' ability to adapt to unexpected changes. Humans can quickly and complia ...

EPFL2022

Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers

David Atienza Alonso, Marina Zapater Sancho, Ali Pahlevan, Darong Huang, Luis Maria Costero Valero

Computing servers play a key role in the development and process of emerging compute-intensive applications in recent years. However, they need to operate efficiently from an energy perspective viewpoint, while maximizing the performance and lifetime of th ...

2022

Sampling-Based AQP in Modern Analytical Engines

Anastasia Ailamaki, Viktor Sanca

As the data volume grows, reducing the query execution times remains an elusive goal. While approximate query processing (AQP) techniques present a principled method to trade off accuracy for faster queries in analytics, the sample creation is often consid ...

ACM2022

Developments on actuator management, plasma state reconstruction, and control on ASDEX Upgrade

Olivier Sauter, Federico Alberto Alfredo Felici, Mengdi Kong, Simon Van Mulders

In present day tokamaks, the role of the control research is to support the physics experiments and to prepare technologies for future devices such as ITER and DEMO. This paper presents the developments done under the MST1 program collaboration on ASDEX Up ...

2021

Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs

Marco Mattavelli, Endri Bezati, Simone Casale Brunet, Anatoly Prihozhy

Large dataflow designs are a result of behavioral specification of modern complex digital systems and/or a result of unfolding and transforming looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resour ...

SPRINGER2020

SpecROP: Speculative Exploitation of ROP Chains

Mathias Josef Payer, Atri Bhattacharyya, Andrés Sánchez Marín

Speculative execution attacks, such as Spectre, reuse code from the victim’s binary to access and leak secret information during speculative execution. Every variant of the attack requires very particular code sequences, necessitating elaborate gadget-sear ...

2020

Task scheduling for highly concurrent analytical and transaction workloads

Anastasia Ailamaki, Iraklis Psaroudakis

Systems and method for a task scheduler with dynamic adjustment of concurrency levels and task granularity are disclosed for improved execution of highly concurrent analytical and transactional systems. The task scheduler can avoid both over commitment and ...

2020

Speculative Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract pa ...

ASSOC COMPUTING MACHINERY2019

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

Boris Robert Grot, Siddharth Gupta

In a drive to maximize resource utilization, today's datacenters are moving to colocation of latency-sensitive and batch workloads on the same server. State-of-the-art deployments, such as those at Google, colocate such diverse workloads even on a single S ...

IEEE2019

FPGA-Assisted Deterministic Routing for FPGAs

Mirjana Stojilovic

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

2019

CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

Felix Schürmann, James Gonzalo King, Pramod Shivaji Kumbhar, Fabien Jonathan Delalondre, Aleksandr Ovcharenko, Jérémy Pierre Benoit Fouriaux

The NEURON simulator has been developed over the past three decades and is widely used by neuroscientists to model the electrical activity of neuronal networks. Large network simulation projects using NEURON have supercomputer allocations that individually ...

2019

Improving Main-memory Database System Performance through Cooperative Multitasking

Georgios Psaropoulos

Database systems access memory either sequentially or randomly. Contrary to sequential access and despite the extensive efforts of computer architects, compiler writers, and system builders, random access to data larger than the processor cache has been s ...

EPFL2019

Fully-Asynchronous Cache-Efficient Simulation of Detailed Neural Networks

Felix Schürmann

Modern asynchronous runtime systems allow the re-thinking of large-scale scientific applications. With the example of a simulator of morphologically detailed neural networks, we show how detaching from the commonly used bulk-synchronous parallel (BSP) exec ...

SPRINGER INTERNATIONAL PUBLISHING AG2019

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

David Atienza Alonso, Pierre-Emmanuel Julien Marc Gaillardon, Marina Zapater Sancho, Xifan Tang, Yasir Mahmood Qureshi, Edouard Giacomin

The need for running complex Machine Learning (ML) algorithms, such as Convolutional Neural Networks (CNNs), in edge devices, which are highly constrained in terms of computing power and energy, makes it important to execute such applications efficiently. ...

2019