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Concept

Transport triggered architecture

Publications associées (12)

EdgeAI-Aware Design of In-Memory Computing Architectures

Marco Antonio Rios

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Green Cryptography and Other Optimisations

Andrea Felice Caforio

The spectral decomposition of cryptography into its life-giving components yields an interlaced network of tangential and orthogonal disciplines that are nonetheless invariably grounded by the same denominator: their implementation on commodity computing p ...

EPFL2023

Attention-based domain adaptation for single-stage detectors

Mathieu Salzmann, Vidit Vidit

While domain adaptation has been used to improve the performance of object detectors when the training and test data follow different distributions, previous work has mostly focused on two-stage detectors. This is because their use of region proposals make ...

SPRINGER2022

From C/C plus plus Code to High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Approximate Decoding for Network Coded Inter-dependent Data

Pascal Frossard, Nikolaos Thomos, Hyung Gon Park

In this paper, we consider decoding of loss tolerant data encoded by network coding and transmitted over error-prone networks. Intermediate network nodes typically perform the random linear network coding in a Galois field and a Gaussian elimination is use ...

Elsevier Science Bv2016

A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures

Marco Mattavelli, Malgorzata Maria Michalska

Maximizing the data throughput is a very common implementation objective for several streaming applications. Such task is particularly challenging for implementations based on many-core and multi-core target platforms because, in general, it implies tackli ...

2015

How to Stop Under-Utilization and Love Multicores

Anastasia Ailamaki, Danica Porobic, Pinar Tözün, Iraklis Psaroudakis, Erietta Liarou

Hardware trends oblige software to overcome three major challenges against systems scalability: (1) taking advantage of the implicit/vertical parallelism within a core that is enabled through the aggressive micro-architectural features, (2) exploiting the ...

2015

Eliminating unscalable communication in transaction processing

Anastasia Ailamaki, Frederick Ryan Johnson, Ippokratis Pandis

Multicore hardware demands software parallelism. Transaction processing workloads typically exhibit high concurrency, and, thus, provide ample opportunities for parallel execution. Unfortunately, because of the characteristics of the application, transacti ...

Springer Verlag2014

Architecture of a Real-Time Platform Independant GPS L1 Software Receiver

Personal digital assistants or mobile phones applications are not anymore restricted to multimedia or wireless communications, but have been extended to handle Global Positioning System (GPS) functionalities. Consequently, the growing market of GPS capable ...

EPFL2010

Algorithm/Architecture Co-Exploration of Visual Computing: Overview and Future Perspectives

Marco Mattavelli

Concurrently exploring both algorithmic and architectural optimizations is a new design paradigm. This survey paper addresses the latest research and future perspectives on the simultaneous development of video coding, processing, and computing algorithms ...

2009

Joint Hardware-Software Leakage Minimization Approach for the Register File of VLIW Embedded Architectures

Giovanni De Micheli, David Atienza Alonso, José Luis Ayala Rodrigo

New applications demand very high processing power when run on embedded systems. Very Long Instruction Word (VLIW) architectures have emerged as a promising alternative to provide such processing capabilities under the given energy budget. However, in this ...

2008

Processeur à haut degré de parallélisme basé sur des composantes sérielles

Ralph Hoffmann

Nowaday, the world of processors is still dominated by the RISC architectures, which foundations have been laid down in the 70's. The RISC concept may be summarized by one word : simplicity. With this concept, much simpler architectures are born, in partic ...

EPFL2004