Concept

Memory geometry

Publications associées (20)

Antiferroelectric Multilayers Devices: a Platform for Energy and Information Storage

This work demonstrates a multifunctional platform that integrates energy storage and multi-bit memory capabilities using multilayer structures composed of antiferroelectric (AFE) Si:HfO2 layers with interleaved dielectric (DE) layers. We have fabricated multilayer AFE/dielectric capacitors with ultrathin 1 nm Al2O3 DE layers between the functional 10 nm AFE layers with up to 4 layers of Al2O3 and 4 layers of AFE, exploiting the internal built-in electric fields, with energy storage density up to 50 J/cm3, a

Institute of Electrical and Electronics Engineers (IEEE)2026

Gem5-AcceSys: Enabling System-Level Exploration of Standard Interconnects for Novel Accelerators

The growing demand for efficient, high-performance processing in machine learning (ML) and image processing has made hardware accelerators, such as GPUs and Data Streaming Accelerators (DSAs), increasingly essential. These accelerators enhance ML and image processing tasks by offloading computation from the CPU to dedicated hardware. These accelerators rely on interconnects for efficient data transfer, making interconnect design crucial for system-level performance. This paper introduces Gem5-AcceSys, an in

2025

OSKAR: Omnimodal Self-supervised Knowledge Abstraction and Representation

Alexandre Massoud Alahi

We present OSKAR, the first multimodal foundation model based on bootstrapped latent feature prediction. Unlike generative or contrastive methods, it avoids memorizing unnecessary details (e.g., pixels), and does not require negative pairs, large memory banks, or hand-crafted augmentations. We propose a novel pretraining strategy: given masked tokens from multiple modalities, predict a subset of missing tokens per modality, supervised by momentum-updated uni-modal target encoders. This design efficiently ut

2025

On-chip decoder and method for decoding neural activity, brain implant comprising the same and prosthetic system comprising the brain implant

The present invention concerns an on-chip decoder (ocD), a brain implant, a prosthetic system and a method for decoding the task-related brain activity from multi-unit recordings of groups of neurons in a brain area and convert it into digital data usable by a classifier generating data labels corresponding to task-related information processed by said brain area, wherein said decoder uses multi-unit threshold crossing rates, called neural activity, subdivided into channels and time slots representing featu

2025

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TLBs used in general-purpose CPUs. Recent research proposals advocate a number of restrictions on virtual-to-physical address mappings in order to reduce the TLB size or increase its reach. However, such restrictions are unattractive because they forgo many

2020

Adaptive NUMA-aware data placement and task scheduling for analytical workloads in main-memory column-stores

Non-uniform memory access (NUMA) architectures pose numerous performance challenges for main-memory column-stores in scaling up analytics on modern multi-socket multi-core servers. A NUMA-aware execution engine needs a strategy for data placement and task scheduling that prefers fast local memory accesses over remote memory accesses, and avoids an imbalance of resource utilization, both CPU and memory bandwidth, across sockets. State-of-the-art systems typically use a static strategy that always partitions

VLDB Endowment2016

Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric

Mihai Adrian Ionescu

The implementation and operation of the nonvolatile ferroelectric memory (NVM) tunnel field effect transistors with silicon-doped HfO2 is proposed and theoretically examined for the first time, showing that ferroelectric nonvolatile tunnel field effect transistor (Fe-TFET) can operate as ultra-low power nonvolatile memory even in aggressively scaled dimensions. A Fe-TFET analytical model is derived by combining the pseudo 2-D Poisson equation and Maxwell’s equation. The model describes the Fe-TFET behavior

2016

Robust scalable high throughput production of monodisperse drops

Esther Amstad

Monodisperse drops with diameters between 20 mu m and 200 mu m can be used to produce particles or capsules for many applications such as for cosmetics, food, and biotechnology. Drops composed of low viscosity fluids can be conveniently made using microflu ...

Royal Society of Chemistry2016

A 4x9 Gb/s 1 pJ/b NRZ/Multi-Tone Serial-Data Transceiver with Crosstalk Reduction Architecture for Multi-Drop Memory Interfaces in 40nm CMOS

Yusuf Leblebici

An aggregated 36 Gb/s low power 4-lanes mixed NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40nm CMOS technology. The proposed architecture achieves 1 pJ/bit power efficiency in the entire link (TX + RX) for an MDB channel with 45 dB loss at 3 GHz. The multi-tone nature of the proposed transceiver is employed to properly reduce crosstalk (Xtalk) induced noise and to improve overall power efficiency. © 2015 JSAP.

2015

Challenges of Memory Management on Modern NUMA Systems

Baptiste Joseph Eustache Lepers, Mohammad Dashti Rahmat Abadi

The latency of memory access times is hence non-uniform, because it depends on where the request originates and where it is destined to go. Such systems are referred to as nonuniform memory access (or NUMA). Current x86 NUMA systems are cache coherent (cal ...

Assoc Computing Machinery2015

Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces

Yusuf Leblebici

A 7.5 Gb/s mixed NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for a MDB channel with 45 dB loss at 2.5 GHz. The transmitted spectrum is composed of baseband (BB) and I /Q sub-bands with the ability to match the modulation frequency of the entire transceiver (TRX) with respect to the channel r

Institute of Electrical and Electronics Engineers2015

Network-on-chip using request and reply trees for low-latency processor-memory communication

Babak Falsafi, Boris Robert Grot

A Network-On-Chip (NOC) organization comprises a die having a cache area and a core area, a plurality of core tiles arranged in the core area in a plurality of subsets, at least one cache memory bank arranged in the cache area, whereby the at least one cac ...

2014

3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory

Yusuf Leblebici

Shared L1 memories are of interest for tightly- coupled processor clusters in programmable accelerators as they provide a convenient shared memory abstraction while avoiding cache coherence overheads. The performance of a shared-L1 memory critically depends on the architecture of the low-latency interconnect between processors and memory banks, which needs to provide ultra-fast access to the largest possible L1 working set. The advent of 3D technology provides new opportunities to improve the interconnect d

2012

Surface potential compact model for embedded flash devices oriented to IC memory design

Yusuf Leblebici, Alexandre Schmid

A surface potential-based model for embedded flash memory cells has been developed with the purpose of providing a comprehensive physical understanding of the device operation suitable for performance optimization in memory circuit design. The device equations account for charge balance effects on the isolated floating gate node and parasitic couplings between the terminals of the memory cell. The compact model supports DC, AC and transient analyses, including program/erase bias scalability, drain disturb a

Pergamon-Elsevier Science Ltd2012

3D Integration Technology for Lab-on-a-Chip Applications

Yüksel Temiz

This study adds a new dimension to lab-on-a-chip systems by employing three-dimensional (3D) integration technology for improved performance, higher functionality, and on-chip computational power. Despite the extensive amount of current research on 3D memo ...

EPFL2012

The Gigavision Camera

Martin Vetterli, Sabine Süsstrunk, Luciano Sbaiz

We study a new image device called gigavision camera or the gigapixel digital film camera. The main differences between a conventional and a gigavision camera are that the pixels of the latter are binary and orders of magnitude smaller. A gigavision camera can be built using standard memory chip technology, where each memory bit is designed to be light sensitive. A conventional gray level image can be obtained from the binary gigavision image by low-pass filtering and sampling. The main advantage of the gig

2010

Memory refreshing device

The cell assembly (10) refreshment method has a mechanism (22) acting simultaneously on all the cells. The same refreshment signal is applied having a differencing effect following each cell state.

2003

Speaker-Dependent Speech Recognition Based on Phone-Like Units Models --- Application to Voice Dialing

Hervé Bourlard

This paper presents a speaker dependent speech recognition with application to voice dialing. This work has been developed under the constraints imposed by voice dialing applications, i.e., low memory requirements and limited training material. Two methods for producing speaker dependent word baseforms based on Phone Like Units (PLU) are presented and compared: (1) a classical vector quantizer is used to divide the space into regions associated with PLUs; (2) a speaker independent hybrid HMM/MLP recognizer

IDIAP1996

On a Markovian approach for modeling passive solar devices

Thomas Liebling

Stochastic models for the analysis of the energy and thermal comfort performances of passive solar devices have benn increasingly studied for over a decade. A new approach to thermal building modelling, based on Markov chains, is proposed here to combine both the accuracy of traditional dynamic simulation with the practical advantages of simplified methods. A main difficulty of the Markovian approach is the discretization of the system variables. Efficient procedures have been performed to carry out this di

1991

Design and analysis techniques for dynamic current mirrors

Today's world of electronics becomes more and more digital and therefore CMOS becomes the dominant technology. A CMOS process compared to a bipolar process offers several advantages, mainly a low power consumption which is important for portable systems powered by batteries or for large systems. Another point is the smaller device geometries, which increase the number of gates that can be packed on a single chip. Parallel to the increasing digital domain the analog field persists, because the origin of phys

EPFL1990

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Publications associées (20)

On-chip decoder and method for decoding neural activity, brain implant comprising the same and prosthetic system comprising the brain implant

2025

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

2020

Adaptive NUMA-aware data placement and task scheduling for analytical workloads in main-memory column-stores

VLDB Endowment2016

Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric

Mihai Adrian Ionescu

2016

Robust scalable high throughput production of monodisperse drops

Esther Amstad

Royal Society of Chemistry2016

A 4x9 Gb/s 1 pJ/b NRZ/Multi-Tone Serial-Data Transceiver with Crosstalk Reduction Architecture for Multi-Drop Memory Interfaces in 40nm CMOS

Yusuf Leblebici

2015