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Concept

PCI Express

Publications associées (24)

3D diffractive optics for linear interconnects and nonlinear processing

Niyazi Ulas Dinç

The optical domain presents potential avenues for enhancing both computing and communication due to its inherent properties of bandwidth, parallelism, and energy efficiency. This research focuses on harnessing 3-Dimensional (3D) diffractive optics for nove ...

EPFL2024

Chaosity: Understanding Contemporary NUMA-architectures

Anastasia Ailamaki, Viktor Sanca, Syed Mohammad Aunn Raza, Hamish Mcniece Hill Nicholson, Andreea Nica

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

2023

A synthetic phase-contrast imaging diagnostic with spatial filtering for gyrokinetic simulations

Stefano Coda, Stephan Brunner, Gabriele Merlo, Justin Richard Ball, Aylwin Iantchenko

A Phase-contrast imaging (PCI) diagnostic provides measurements of line-integrated electron density fluctuations. Localisation along the laser beam path can be achieved with a spatial filter that selects the wave-vector directions of the fluctuations contr ...

2023

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Mirjana Stojilovic, Stefan Nikolic, Shashwat Shrivastava

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

IEEE2023

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Arin Can Ülkü, Andrei Ardelean, Paul Mos, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

GPU-accelerated data management under the test of time

Anastasia Ailamaki, Periklis Chrysogelos, Angelos Christos Anadiotis, Panagiotis Sioulas, Syed Mohammad Aunn Raza

GPUs are becoming increasingly popular in large scale data center installations due to their strong, embarrassingly parallel, processing capabilities. Data management systems are riding the wave by using GPUs to accelerate query execution, mainly for analy ...

2020

Scalable Marine Bus-Tie Switch for Switchboard Interconnections

Drazen Dujic, Gabriele Ulissi

DC power distribution systems in marine applications are in the process of being established as the preferred solution for shipboard power distribution systems. This paper presents a bus-tie switch topology for the protection of such systems. The device is ...

2020

Four Quadrant Bus-Tie Switch for Protection of Shipboard Power Systems

Drazen Dujic, Gabriele Ulissi

The desire to increase the voltage of DC shipboard power distribution networks to the medium voltage level derives from the pressure to reduce the operating costs of such systems by increasing their efficiency. Solid state bus-tie switches are accepted to ...

IEEE2020

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Yusuf Leblebici, Andreas Peter Burg, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Ilter Ozkaya, Gain Kim, Cosimo Aprile

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed a ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Pythia: Remote Oracles for the Masses

Mathias Josef Payer

Remote Direct Memory Access (RDMA) is a technology that allows direct access from the network to a machine's main memory without involving its CPU. RDMA offers low-latency, high-bandwidth performance and low CPU utilization. While RDMA provides massive per ...

USENIX ASSOC2019

Hardware-conscious Hash-Joins on GPUs

Anastasia Ailamaki, Raja Appuswamy, Manolis Karpathiotakis, Periklis Chrysogelos, Panagiotis Sioulas

Traditionally, analytical database engines have used task parallelism provided by modern multisocket multicore CPUs for scaling query execution. Over the past few years, GPUs have started gaining traction as accelerators for processing analytical queries d ...

IEEE2019

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Yusuf Leblebici, Volkan Cevher, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Cosimo Aprile

This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme, which combines analog filters and decision-feedback crosstalk compensation on the receiver (RX) side ...

2018

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

Andreas Peter Burg, Thomas Toifl, Lukas Kull

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105 orilV at a supply voltage of 0.7 V, corresponding to an energy efficiency ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

Multi-Tone Signaling and ADC-Based Digital Receiver for High-Speed Wireline Serial Links

Gain Kim

The exponential growth of Internet traffic and related demands for higher communication speed pushes processor-to-processor and processor-to-memory interconnects to provide further higher data-rate. Often time, processor-to-memory interconnectsâ speed is ...

EPFL2018

Exploring the interoperability of remote GPGPU virtualization using rCUDA and directive-based programming models

Judit Planas Carbonell

Directive-based programming models, such as OpenMP, OpenACC, and OmpSs, enable users to accelerate applications by using coprocessors with little effort. These devices offer significant computing power, but their use can introduce two problems: an increase ...

SPRINGER2018

Design Guidelines for High-Performance SCM Hierarchies

Babak Falsafi, Edouard Bugnion, Javier Picorel Obando, Alexandros Daglis, Mark Johnathon Sutherland, Dmitrii Ustiugov

With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a fewfactors of DRAM. Nevertheless, the latency-sensitive nature of memory-residen ...

ACM2018

Learning-Based Hardware Design for Data Acquisition Systems

Cosimo Aprile

This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conc ...

EPFL2018

Architectural Modeling of a Multi-Tone/Single-Sideband Serial Link Transceiver for Lossy Wireline Data Links

Yusuf Leblebici, Gain Kim

This paper presents a serial link transceiver (TRX) architecture that enables high-speed data transmission over a lossy backplane channel without the presence of equalization circuits. The proposed architecture employs multi-tone signaling to reduce inter- ...

Ieee2016

A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

Yusuf Leblebici, Volkan Cevher, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Ilter Ozkaya, Cosimo Aprile

This work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a cross continuous-time linear equalizer (XCTLE) to remove FEXT by nearest aggressors within the channe ...

2015

Ultra Fine-Pitch TSV Technology for Ultra-Dense High-Q RF Inductors

Mihai Adrian Ionescu, Montserrat Fernandez-Bolanos Badia, Wolfgang Amadeus Vitale

We demonstrate that fine-pitch TSV technology can be exploited to fabricate micro-inductors on high resistivity substrate, with record-high inductance per area and preserving their performance at GHz frequencies. We report an extensive experimental study o ...

2015