Concept

Bulldozer (microarchitecture)

Publications associées (27)

A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures

Marco Mattavelli, Malgorzata Maria Michalska

Maximizing the data throughput is a very common implementation objective for several streaming applications. Such task is particularly challenging for implementations based on many-core and multi-core target platforms because, in general, it implies tackli ...

2015

Shared Frontend for Manycore Server Processors

Ilknur Cansu Kaynak

Instruction-supplymechanisms, namely the branch predictors and instruction prefetchers, exploit recurring control flow in an application to predict the applicationâ s future control flow and provide the core with a useful instruction stream to execute in ...

EPFL2015

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Paolo Ienne, Andreas Peter Burg, David Novo Bruna, Georgios Karakonstantis, Gabriel Falcao Paiva Fernandes, Madhura Purnaprajna

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementatio ...

Assoc Computing Machinery2015

How to Stop Under-Utilization and Love Multicores

Anastasia Ailamaki, Danica Porobic, Pinar Tözün, Iraklis Psaroudakis, Erietta Liarou

Hardware trends oblige software to overcome three major challenges against systems scalability: (1) taking advantage of the implicit/vertical parallelism within a core that is enabled through the aggressive micro-architectural features, (2) exploiting the ...

2015

Approximate Compressed Sensing: Ultra-Low Power Biosignal Processing via Aggressive Voltage Scaling on a Hybrid Memory Multi-core Processor

David Atienza Alonso, Pierre Vandergheynst, Luca Benini, Hossein Mamaghanian

Technology scaling enables the design of low cost biosignal processing chips suited for emerging wireless body-area sensing applications. Energy consumption severely limits such applications and memories are becoming the energy bottleneck to achieve ultra- ...

IEEE/ACM Press2014

Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

Giovanni De Micheli, Siang-Yun Lee

The advent of 3-D fabrication technology makes it possible to stack a large amount of last-level cache memory onto a multi-core die to reduce off-chip memory accesses and, thus, increases system performance. However, the higher power density (i.e., power d ...

2014

How to Stop Under-Utilization and Love Multicores

Anastasia Ailamaki, Danica Porobic, Pinar Tözün, Iraklis Psaroudakis, Erietta Liarou

Designing scalable transaction processing systems on modern hardware has been a challenge for almost a decade. Hardware trends oblige software to overcome three major challenges against systems scalability: (1) Exploiting the abundant thread-level parallel ...

2014