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Concept

No instruction set computing

Publications associées (25)

Do Children Adapt Their Perspective to a Robot When They Fail to Complete a Task?

Pierre Dillenbourg, Elmira Yadollahi

Spatial understanding and communication are essential skills in human interaction. An adequate understanding of others' spatial perspectives can increase the quality of the interaction, both perceptually and cognitively. In this paper, we take the first st ...

Assoc Computing Machinery2022

CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

Felix Schürmann, James Gonzalo King, Pramod Shivaji Kumbhar, Fabien Jonathan Delalondre, Aleksandr Ovcharenko, Jérémy Pierre Benoit Fouriaux

The NEURON simulator has been developed over the past three decades and is widely used by neuroscientists to model the electrical activity of neuronal networks. Large network simulation projects using NEURON have supercomputer allocations that individually ...

2019

A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Mathias Soeken, Giulia Meuli

Solid-state resistive switches have recently enabled low-power, scalable, non-volatile memories. Their proven intrinsic logic operation, allowing design of in-memory computing systems, attracted the attention of the research community. A Programmable Logic ...

2017

Unified prefetching into instruction cache and branch target buffer

Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak

A system and method of coupling a Branch Target Buffer (BTB) content of a BTB with an instruction cache content of an instruction cache. The method includes: tagging a plurality of target buffer entries that belong to branches within a same instruction blo ...

2017

The effects of haptic-virtual reality game therapy on brain-motor coordination for children with hemiplegia: A pilot study

Mohamed Bouri

Children with hemiplegia have movements' difficulties especially in their upper limbs, these difficulties occur due to the loss of the communication between the brain and the affected side of the body. In this study, visual, audio, and tactile stimulation ...

IEEE2017

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Jeremy Hugues-Felix Constantin, Thomas Christoph Müller, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

Jeremy Hugues-Felix Constantin

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumpti ...

EPFL2016

Shared Frontend for Manycore Server Processors

Ilknur Cansu Kaynak

Instruction-supplymechanisms, namely the branch predictors and instruction prefetchers, exploit recurring control flow in an application to predict the applicationâ s future control flow and provide the core with a useful instruction stream to execute in ...

EPFL2015

Transactions Chasing Scalability and Instruction Locality on Multicores

Pinar Tözün

For several decades, online transaction processing (OLTP) has been one of the main server applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Recent hardware trends oblige s ...

EPFL2014

Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis

Ahmed Yasir Dogan

According to the World Health Organization, lifestyle-related diseases, e.g., cardiovascular diseases are the major cause of mortality worldwide. An accurate and continuous medical supervision is highly required for diagnosis and treatment of such diseases ...

EPFL2013

Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors

Edoardo Charbon, Claudio Favi, Ties Jan Henderikus Kluter, Christian Mester

We propose a technique to localize computation in Instruction Set Extensions (ISEs) that are clocked at very high speed with respect to the processor. In order to save power, data to and from Custom Instruction Units (CIUs) is synchronized via an optical s ...

2012

Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems

David Atienza Alonso, Andreas Peter Burg, Martino Ruggiero, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan

Personal health monitoring systems can offer a cost-effective solution for human healthcare. To extend the lifetime of health monitoring systems, we propose a near-threshold ultra-low- power multi-core architecture featuring low-power cores, yet capable of ...

ACM and IEEE Press2012

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

Andreas Peter Burg, Jeremy Hugues-Felix Constantin

In this paper, we investigate the benefits of instruction set extensions (ISEs) on a 16-bit microcontroller architecture for software implementations of cryptographic hash functions, using the example of the five SHA-3 final round candidates. We identify t ...

Ieee2012

Low-power processor architecture exploration for online biomedical signal analysis

David Atienza Alonso, Andreas Peter Burg, Luca Benini, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan

In this study, the authors explore sequential and parallel processing architectures, utilising a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations ...

Inst Engineering Technology-Iet2012

Simulation of High-Performance Memory Allocators

David Atienza Alonso

This study presents a single-core and a multi-core processor architecture for health monitoring systems where slow biosignal events and highly parallel computations exist. The single-core architecture is composed of a processing core (PC), an instruction m ...

Elsevier2011

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing

David Atienza Alonso, Andreas Peter Burg, Luca Benini, Ahmed Yasir Dogan

Springer-Verlag Heidelberg2011

Architecture of a Real-Time Platform Independant GPS L1 Software Receiver

Personal digital assistants or mobile phones applications are not anymore restricted to multimedia or wireless communications, but have been extended to handle Global Positioning System (GPS) functionalities. Consequently, the growing market of GPS capable ...

EPFL2010

Memory Organization and Data Layout for Instruction Set Extensions with Architecturally Visible Storage

Yusuf Leblebici, Paolo Ienne, Philip Brisk, Panagiotis Athanasopoulos

Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional units (CFUs). Adoption of the optimal ISE for an application would, in many cas ...

2009

A hardware-software codesign framework for cellular computing

Pierre-André Mudry

Until recently, the ever-increasing demand of computing power has been met on one hand by increasing the operating frequency of processors and on the other hand by designing architectures capable of exploiting parallelism at the instruction level through h ...

EPFL2009

A putative implication for fronto-parietal connectivity in out-of-body experiences

Olaf Blanke, Christine Mohr

Self-processing has been related to the prefrontal cortex (PFC) and the temporo-parietal junction (TPJ) as well as to their connectivity. So far, out-of-body experiences (OBEs), impressive transient deviations of intact bodily self-integration, could be as ...

Elsevier Masson2009