Publication

On the Performance of Delegation over Cache-Coherent Shared Memory

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Virtual Memory (VM) is a critical programming abstraction that is widely used in various modern computing platforms. With the rise of datacenter computing and birth of planet-scale online services, the semantic and capacity requirements from memory have ev ...

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Chaosity: Understanding Contemporary NUMA-architectures

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Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

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Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

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Cycles are one of the fundamental subgraph patterns and being able to enumerate them in graphs enables important applications in a wide variety of fields, including finance, biology, chemistry, and network science. However, to enable cycle enumeration in r ...

Assoc Computing Machinery2023

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Accessing input data is a critical operation in data analytics: i) slow data access significantly degrades performance, and ii) storing everything in the fastest medium, i.e., memory, incurs high operational and hardware costs. Further, while GPUs offer in ...

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uKharon: A Membership Service for Microsecond Applications

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USENIX Association2023

Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers

David Atienza Alonso, Ali Pahlevan, Marina Zapater Sancho, Luis Maria Costero Valero, Darong Huang

Computing servers play a key role in the development and process of emerging compute-intensive applications in recent years. However, they need to operate efficiently from an energy perspective viewpoint, while maximizing the performance and lifetime of th ...

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Scalable Fine-Grained Parallel Cycle Enumeration Algorithms

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Enumerating simple cycles has important applications in computational biology, network science, and financial crime analysis. In this work, we focus on parallelising the state-of-the-art simple cycle enumeration algorithms by Johnson and Read-Tarjan along ...

arXiv2022

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In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the "memory wall" are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recen ...

IEEE2022

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

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The hardware complexity of modern machines makes the design of adequate programming models crucial for jointly ensuring performance, portability, and productivity in high-performance computing (HPC). Sequential task-based programming models paired with adv ...

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How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

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String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

Rethinking Software Runtimes for Disaggregated Memory

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Disaggregated memory can address resource provisioning inefficiencies in current datacenters. Multiple software runtimes for disaggregated memory have been proposed in an attempt to make disaggregated memory practical. These systems rely on the virtual mem ...

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Micro-architectural Analysis of Database Workloads

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Database workloads have significantly evolved in the past twenty years. Traditional database systems that are mainly used to serve Online Transactional Processing (OLTP) workloads evolved into specialized database systems that are optimized for particular ...

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Micro-architectural analysis of in-memory OLTP: Revisited

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Micro-architectural behavior of traditional disk-based online transaction processing (OLTP) systems has been investigated extensively over the past couple of decades. Results show that traditional OLTP systems mostly under-utilize the available micro-archi ...

2021

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Paolo Ienne, Mikhail Asiatici

Efficient large-scale graph processing is crucial to many disciplines. Yet, while graph algorithms naturally expose massive parallelism opportunities, their performance is limited by the memory system because of irregular memory accesses. State-of-the-art ...

IEEE COMPUTER SOC2021

Rebooting Virtual Memory with Midgard

Babak Falsafi, Atri Bhattacharyya, Siddharth Gupta, Mathias Josef Payer, Yunho Oh, Abhishek Bhattacharjee

Computer systems designers are building cache hierarchies with higher capacity to capture the ever-increasing working sets of modern workloads. Cache hierarchies with higher capacity improve system performance but shift the performance bottleneck to addres ...

2021

NrOS: Effective Replication and Sharing in an Operating System

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Writing a correct operating system kernel is notoriously hard. Kernel code requires manual memory management and type-unsafe code and must efficiently handle complex, asynchronous events. In addition, increasing CPU core counts further complicate kernel de ...

USENIX ASSOC2021

Leaking Secrets Through Compressed Caches

Daniel Felipe Forero Sanchez

We offer the first security analysis of cache compression, a promising architectural technique that is likely to appear in future mainstream processors. We find that cache compression has novel security implications because the compressibility of a cache l ...

IEEE COMPUTER SOC2021

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

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Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

EPFL2021

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is an important part of database and MapReduce applications; however, it has not been studied as extensively as sorting of fixed-length keys. Handling variable-length keys in hardware is challenging and it is no surprise that no string sorte ...

IEEE COMPUTER SOC2020

The NEBULA RPC-Optimized Architecture

Babak Falsafi, Alexandros Daglis, Mark Johnathon Sutherland, Dionysios Pnevmatikatos, Siddharth Gupta

Large-scale online services are commonly structured as a network of software tiers, which communicate over the datacenter network using RPCs. Ongoing trends towards software decomposition have led to the prevalence of tiers receiving and generating RPCs wi ...

2020