EdgeAI-Aware Design of In-Memory Computing Architectures

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The desire and ability to place AI-enabled applications on the edge has grown significantly in recent years. However, the compute-, area-, and power-constrained nature of edge devices are stressed by the needs of the AI-enabled applications, due to a gener ...

The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the use ...

Machine learning algorithms such as Convolutional Neural Networks (CNNs) are characterized by high robustness towards quantization, supporting small-bitwidth fixed-point arithmetic at inference time with little to no degradation in accuracy. In turn, small ...

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

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The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

In the past decades, a significant increase of the transistor density on a chip has led to exponential growth in computational power driven by Moore's law. To overcome the bottleneck of traditional von-Neumann architecture in computational efficiency, effo ...

Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing acceleration relies on the quality of mapping: how efficiently the CIL is c ...

The field of biometrics, and especially face recognition, has seen a wide-spread adoption the last few years, from access control on personal devices such as phones and laptops, to automated border controls such as in airports. The stakes are increasingly ...

Multiple tensor-times-matrix (Multi-TTM) is a key computation in algorithms for computing and operating with the Tucker tensor decomposition, which is frequently used in multidimensional data analysis. We establish communication lower bounds that determine ...

Fluorescence lifetime imaging (FLI) has been receiving increased attention in recent years as a powerful diagnostic technique in biological and medical research. However, existing FLI systems often suffer from a tradeoff between processing speed, accuracy, ...

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In this PhD manuscript, we explore optimisation phenomena which occur in complex neural networks through the lens of

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The design of low-power wearables for the biomedical domain has received a lot of attention in recent decades, as technological advances in chip manufacturing have allowed real-time monitoring of patients using low-complexity ML within the mW range. Despit ...

EdgeAI-Aware Design of In-Memory Computing Architectures

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Exploring High-Performance and Energy-Efficient Architectures for Edge AI-Enabled Applications

Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD

Highly Parallel RTL Simulation

Secure Interface Design Leveraging Hardware/Software Support

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Towards Scalable Electronics: Synthetic 2D Materials for Large-Area 2D Circuit Integration

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs

Performing and Detecting Backdoor Attacks on Face Recognition Algorithms

COMMUNICATION LOWER BOUNDS AND OPTIMAL ALGORITHMS FOR MULTIPLE TENSOR-TIMES-MATRIX COMPUTATION

Coupling a recurrent neural network to SPAD TCSPC systems for real-time fluorescence lifetime imaging

Infusing structured knowledge priors in neural models for sample-efficient symbolic reasoning

Voices from the Frontline: Revealing the AI Practitioners' viewpoint on the European AI Act

Deep Learning Theory Through the Lens of Diagonal Linear Networks

Assessment framework for deepfake detection in real-world situations

Digital Twins of Stone Masonry Buildings for Damage Assessment

The 2024 Magnonics Roadmap

BiomedBench: A benchmark suite of TinyML biomedical applications for low-power wearables