Publication

Multi-Area Unit Scheduling and Reserve Allocation Under Wind Power Uncertainty

Related publications (24)

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Mirjana Stojilovic, David Dervishi, Dina Gamaleldin Ahmed Shawky Mahmoud

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

2022

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

High-Level Synthesis of Dynamically Scheduled Circuits

Lana Josipovic

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

EPFL2021

Improving Main-memory Database System Performance through Cooperative Multitasking

Georgios Psaropoulos

Database systems access memory either sequentially or randomly. Contrary to sequential access and despite the extensive efforts of computer architects, compiler writers, and system builders, random access to data larger than the processor cache has been s ...

EPFL2019

Multi-Arm Self-Collision Avoidance: A Sparse Solution for a Big Data Problem

Aude Billard, Seyed Sina Mirrazavi Salehian, Nadia Barbara Figueroa Fernandez

In this work, we propose a data-driven approach for real-time self-collision avoidance in multi-arm systems. The approach consists of modeling the regions in joint-space that lead to collisions via a Self-Collision Avoidance (SCA) boundary and use it as a ...

2018

Dispatch and Primary Frequency Control with Electrochemical Storage: a System-wise Verification

Mario Paolone, Mokhtar Bozorg, Fabrizio Sossan, Yihui Zuo

Uncertainty levels in forecasting of renewable generation and demand are known to affect the amount of reserve required to operate the power grid with a given level of reliability. In this paper, we quantify the effects on the system reserve and reliabilit ...

IEEE2018

Characterization of the Impact of Hardware Islands on OLTP

Anastasia Ailamaki, Pinar Tözün, Ippokratis Pandis, Danica Porobic, Miguel Sérgio De Oliveira Branco

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and processor caches, which causes variability in the communication costs. Unfortunately, database sys ...

Springer Verlag2016

Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing

David Atienza Alonso, Ahmed Yasir Dogan, Andreas Peter Burg, Jeremy Hugues-Felix Constantin

A multi-core architecture with ultra-low power consumption is needed for a wide variety of applications, especially in the bio-medical domain. In this patent, an ultra-low power multi-core architecture is presented: it is composed of one or more cores, sev ...

2014

Transactions Chasing Scalability and Instruction Locality on Multicores

Pinar Tözün

For several decades, online transaction processing (OLTP) has been one of the main server applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Recent hardware trends oblige s ...

EPFL2014

Scalable Simulation Methodologies for Many-Core Heterogeneous Systems

Shivani Raghav

With increasing complexity and performance demands of emerging compute-intensive data-parallel workloads, many-core computing systems are becoming a popular trend in computer design. Fast and scalable simulation methods are needed to make meaningful predic ...

EPFL2014

Task Scheduling for Highly Concurrent Analytical and Transactional Main-Memory Workloads

Anastasia Ailamaki, Iraklis Psaroudakis

Task scheduling typically employs a worker thread per hardware context to process a dynamically changing set of tasks. It is an appealing solution to exploit modern multi-core processors, as it eases parallelization and avoids unnecessary context switches ...

2013

Reserve services management in multi-area power system under uncertainty

Ali Ahmadi Khatir

The reserve is a service traded in the market to counteract unpredictable changes in system conditions. The efficient market-clearing procedure relies on economic criteria while maintaining the system security by means of a proper reserve management progra ...

EPFL2013

Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis

Ahmed Yasir Dogan

According to the World Health Organization, lifestyle-related diseases, e.g., cardiovascular diseases are the major cause of mortality worldwide. An accurate and continuous medical supervision is highly required for diagnosis and treatment of such diseases ...

EPFL2013

OLTP on Hardware Islands

Anastasia Ailamaki, Pinar Tözün, Ippokratis Pandis, Danica Porobic, Miguel Sérgio De Oliveira Branco

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and to the processor caches, which causes variability in the communication costs. Unfortunately, datab ...

2012

Approximation Algorithms for Modern Multi-Processor Scheduling Problems

Martin Niemeier

This thesis is devoted to the design and analysis of algorithms for scheduling problems. These problems are ubiquitous in the modern world. Examples include the optimization of local transportation, managing access to concurrent resources like runways at a ...

EPFL2012

Scale-Out Processors

Babak Falsafi, Michael Ferdman, Pejman Lotfi Kamran, Stavros Volos, Al Mutaz Adileh, Dorde Jevdic, Yusuf Onur Koçberber, Javier Picorel Obando, Boris Robert Grot

Scale-out datacenters mandate high per-server throughput to get the maximum benefit from the large TCO investment. Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommodated by ...

Ieee2012

Toward Predictable Performance in Software Packet-Processing Platforms

Aikaterini Argyraki, Mihai Dobrescu

To become a credible alternative to specialized hardware, general-purpose networking needs to offer not only flexibility, but also predictable performance. Recent projects have demonstrated that general-purpose multicore hardware is capable of high-perform ...

2012

TurboTag: Lookup Filtering to Reduce Coherence Directory Power

Babak Falsafi, Michael Ferdman, Daniel Crisan, Pejman Lotfi Kamran

On-chip coherence directories of today’s multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary lookups when running commercial server and scientific workloads. These workloads have ...

ACM2010

A hardware-software codesign framework for cellular computing

Pierre-André Mudry

Until recently, the ever-increasing demand of computing power has been met on one hand by increasing the operating frequency of processors and on the other hand by designing architectures capable of exploiting parallelism at the instruction level through h ...

EPFL2009