Multi-Area Unit Scheduling and Reserve Allocation Under Wind Power Uncertainty

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

Integrated Flow Cell Array (FCA) technology promises to address the power delivery and heat dissipation challenges in three-dimensional Multi Processor Systems-on-Chips (3D MPSoCs) by providing combined inter-tier liquid cooling and power generation capabi ...

Database systems access memory either sequentially or randomly. Contrary to sequential access and despite the extensive efforts of computer architects, compiler writers, and system builders, random access to data larger than the processor cache has been s ...

In this work, we propose a data-driven approach for real-time self-collision avoidance in multi-arm systems. The approach consists of modeling the regions in joint-space that lead to collisions via a Self-Collision Avoidance (SCA) boundary and use it as a ...

Uncertainty levels in forecasting of renewable generation and demand are known to affect the amount of reserve required to operate the power grid with a given level of reliability. In this paper, we quantify the effects on the system reserve and reliabilit ...

The optimal power flow (OPF) problem, a fundamental problem in power systems, is generally nonconvex and computationally challenging for networks with an increasing number of smart devices and real-time control requirements. In this paper, we first investi ...

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and processor caches, which causes variability in the communication costs. Unfortunately, database sys ...

A multi-core architecture with ultra-low power consumption is needed for a wide variety of applications, especially in the bio-medical domain. In this patent, an ultra-low power multi-core architecture is presented: it is composed of one or more cores, sev ...

For several decades, online transaction processing (OLTP) has been one of the main server applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Recent hardware trends oblige s ...

With increasing complexity and performance demands of emerging compute-intensive data-parallel workloads, many-core computing systems are becoming a popular trend in computer design. Fast and scalable simulation methods are needed to make meaningful predic ...

Task scheduling typically employs a worker thread per hardware context to process a dynamically changing set of tasks. It is an appealing solution to exploit modern multi-core processors, as it eases parallelization and avoids unnecessary context switches ...

The reserve is a service traded in the market to counteract unpredictable changes in system conditions. The efficient market-clearing procedure relies on economic criteria while maintaining the system security by means of a proper reserve management progra ...

According to the World Health Organization, lifestyle-related diseases, e.g., cardiovascular diseases are the major cause of mortality worldwide. An accurate and continuous medical supervision is highly required for diagnosis and treatment of such diseases ...

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and to the processor caches, which causes variability in the communication costs. Unfortunately, datab ...

This thesis is devoted to the design and analysis of algorithms for scheduling problems. These problems are ubiquitous in the modern world. Examples include the optimization of local transportation, managing access to concurrent resources like runways at a ...

Scale-out datacenters mandate high per-server throughput to get the maximum benefit from the large TCO investment. Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommodated by ...

To become a credible alternative to specialized hardware, general-purpose networking needs to offer not only flexibility, but also predictable performance. Recent projects have demonstrated that general-purpose multicore hardware is capable of high-perform ...

Multi-Area Unit Scheduling and Reserve Allocation Under Wind Power Uncertainty

Chat with Graph Search

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

High-Level Synthesis of Dynamically Scheduled Circuits

A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays

Improving Main-memory Database System Performance through Cooperative Multitasking

Multi-Arm Self-Collision Avoidance: A Sparse Solution for a Big Data Problem

Dispatch and Primary Frequency Control with Electrochemical Storage: a System-wise Verification

Real-Time Distributed Algorithms for Nonconvex Optimal Power Flow

Characterization of the Impact of Hardware Islands on OLTP

Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing

Transactions Chasing Scalability and Instruction Locality on Multicores

Scalable Simulation Methodologies for Many-Core Heterogeneous Systems

Task Scheduling for Highly Concurrent Analytical and Transactional Main-Memory Workloads

Reserve services management in multi-area power system under uncertainty

Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis

OLTP on Hardware Islands

Approximation Algorithms for Modern Multi-Processor Scheduling Problems

Scale-Out Processors

Toward Predictable Performance in Software Packet-Processing Platforms