Optimization Methodologies for Complex FPGA-based Signal Processing Systems with CAL

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Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

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Optimization Methodologies for Complex FPGA-based Signal Processing Systems with CAL

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Highly Parallel RTL Simulation

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

EdgeAI-Aware Design of In-Memory Computing Architectures

Scalable constrained optimization

A method and system for optimizing design, implantation, and stimulation protocols of electrodes stimulating the nervous system

Robot Learning using Tensor Networks

Co-Design Optimisation of Morphing Topology and Control of Winged Drones

A ride time-oriented scheduling algorithm for dial-a-ride problems

Mesh-based topology, shape and sizing optimization of ribbed plates

Violation-aware contextual Bayesian optimization for controller performance optimization with unmodeled constraints

SOMOphilic alkyne vs radical-polar crossover approaches: The full story of the azido-alkynylation of alkenes

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD

Optimization Algorithms for Decentralized, Distributed and Collaborative Machine Learning

Augmented Memory: Sample-Efficient Generative Molecular Design with Reinforcement Learning

Adaptive projected variational quantum dynamics

The effect of smooth parametrizations on nonconvex optimization landscapes

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation