Publication

Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes

Andreas Peter Burg, Nicholas Alexander Preyss
2008
Conference Papers

Abstract

We describe a fully reconfigurable low-density parity check (LDPC) decoder for quasi-cyclic (QC) codes. The proposed hardware architecture is able to decode virtually any QC-LDPC code that fits into the allocated memories while achieving high decoding throughput. Our VLSI implementation has been optimized for the IEEE 802.11n standard and achieves a throughput of 780 M bit/s with a core area of 3.39 mm(2) in 0.18 mu m CMOS technology.

Official source

https://infoscience.epfl.ch/entities/publication/dabd25eb-6f87-4fc7-b3a8-12cb695bfe62

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Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes

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