NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration

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Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

Smarty is a fully-reconfigurable on-chip feed-forward artificial neural network (ANN) with ten integrated time-to-digital converters (TDCs) designed in a 16 nm FinFET CMOS technology node. The integration of TDCs together with an ANN aims to reduce system ...

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

This paper proposes a generic and unified model of the power flow (PF) problem for multiterminal hybrid AC/DC networks. The proposed model is an extension of the standard AC-PF. The DC network is treated as an AC one and, in addition to the Slack, PV and P ...

Low-level light detection with high spatial and timing accuracy is a growing area of interest by virtue of applications such as light detection and ranging (LiDAR), biomedical imaging, time-resolved Raman spectroscopy, and quantum applications. Single-phot ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

In this work, we propose an open-hardware low-power coarse-grained reconfigurable array connected to a lightweight microcontroller and enclosed in an application mapping framework. The latter provides complete support to configure kernels in the reconfigur ...

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

Combining optical gain in direct-bandgap III-V materials with tunable optical feedback offered by advanced photonic integrated circuits is key to chip-scale external-cavity lasers (ECL), offering wideband tunability along with low optical linewidths. Exter ...

Vision systems built around conventional image sensors have to read, encode and transmit large quantities of pixel information, a majority of which is redundant. As a result, new computational imaging sensor architectures were developed to preprocess the r ...

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

MALTA is a depleted monolithic active pixel sensor (DMAPS) developed in the Tower Semiconductor 180-nm CMOS imaging process. Monolithic CMOS sensors offer advantages over current hybrid imaging sensors in terms of both increased tracking performance due to ...

Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

To cope with the challenging environment of the planned high luminosity upgrade of the Large Hadron Collider (HL-LHC), scheduled to start operation in 2029, CMS will replace its entire tracking system. The requirements for the tracker are largely determine ...

Fuzzing reliably and efficiently finds bugs in software, including operating system kernels. In general, higher code coverage leads to the discovery of more bugs. This is why most existing kernel fuzzers adopt strategies to generate a series of inputs that ...

NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration

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Highly Parallel RTL Simulation

On-Chip Fully Reconfigurable Artificial Neural Network in 16 nm FinFET for Positron Emission Tomography

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

General and Unified Model of the Power Flow Problem in Multiterminal AC/DC Networks

Advanced Silicon and SWIR Single-Photon Avalanche Diodes: Design, Simulation, and Characterization

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

An Open-Hardware Coarse-Grained Reconfigurable Array for Edge Computing

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Sub-kHz-Linewidth External-Cavity Laser (ECL) With Si3N4 Resonator Used as a Tunable Pump for a Kerr Frequency Comb

Computational Imaging SPAD Cameras

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Radiation Hardness of MALTA2, a Monolithic Active Pixel Sensor for Tracking Applications

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Chaosity: Understanding Contemporary NUMA-architectures

Evaluation of HPK n plus -p planar pixel sensors for the CMS Phase-2 upgrade

ACTOR: Action-Guided Kernel Fuzzing