Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

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Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

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EdgeAI-Aware Design of In-Memory Computing Architectures

Imprecise Store Exceptions

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Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Do Children Adapt Their Perspective to a Robot When They Fail to Complete a Task?

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Boosting Efficiency of External Pipelines by Blurring Application Boundaries

Attention-based domain adaptation for single-stage detectors

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

HPCache: Memory-Efficient OLAP Through Proportional Caching

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers

Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs

Micro-architectural Analysis of Database Workloads

Software Support for Non-Volatile Memory (NVM) Programming