Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Inductive power transfer technology is an attractive solution for medium voltage applications by eliminating the need for high voltage cables or wired connections in general. This paper introduces an inductive power transfer system which has multiple indep ...

In this study, we present a technical and economic assessment of high-current HTS bus bars for primary use in fusion reactors. Our objective is to verify the technical feasibility of such conductors and, for this purpose, we carry out a conceptual design o ...

The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel ...

Sampling has always been at the heart of signal processing providing a bridge between the analogue world and discrete representations of it, as our ability to process data in continuous space is quite limited. Furthermore, sampling plays a key part in unde ...

This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode adaptive background comparator offset calibration scheme. LU-SAR ADCs use multiple co ...

The pedestal structure, edge transport and linear MHD stability have been analyzed in a series of JET with the ITER-like wall hydrogen (H) and deuterium (D) type I ELMy H-mode plasmas. The pedestal pressure is typically higher in D than in H at the same in ...

The aim of this thesis is to implement, analyze and improve the selected low noise clock generation and distribution techniques for ADC implementations. The thesis is divided into two parts. The first part focuses on the sampling phase generation and distr ...

A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) comprising a Track-and-Hold (T/H) switch configured for a sampling of an input voltage in the form of charge onto a capacitor; a Capacitive Digital-to- Analog Converter (CD AC) opera ...

Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver

Chat with Graph Search

Inductive Power Transfer System for Auxiliary Power Supply in Medium Voltage Converters

Technical and economic feasibility study of high-current HTS bus bars for fusion reactors

High-Speed ADC Design and Optimization for Wireline Links

Uncertain Sampling with Certain Priors

An 8-Bit 800 MS/s Loop-Unrolled SAR ADC With Common-Mode Adaptive Background Offset Calibration in 28 nm FDSOI

Isotope dependence of the type I ELMy H-mode pedestal in JET-ILW hydrogen and deuterium plasmas

Low Noise Clock Generation: Modeling, Analysis and Implementation

Asynchronous sar adc with unit length capacitors and constant common mode monotonic switching