Delta Compression of Neural Recordings for High-density CMOS-based Microelectrode Arrays

Recent high-density CMOS-based MEAs contain thousands of electrodes. Hence, an off-chip acquisition system performing data compression prior to visualization and analysis on a computer is required in order to handle the large amount of data generated by active MEAs. Since significant information is discarded with conventional spike detection algorithms, a delta compression algorithm is implemented on a Xilinx Virtex 5 FPGA. An experimental setup is developed in order to verify the functionality of the data acquisition system, implemented on the FPGA platform, independently from the CMOS front-end. It is shown that if the signal-to-noise ratio (SNR) of the input signal is higher or equal to 10 dB, delta compression is suitable for high-density MEAs.