A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

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A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

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Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Highly Parallel RTL Simulation

EdgeAI-Aware Design of In-Memory Computing Architectures

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Imaging sensor device using an array of single-photon avalanche diode photodetectors

Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Chaosity: Understanding Contemporary NUMA-architectures

REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Cooperative Concurrency Control for Write-Intensive Key-Value Workloads

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck