DSPE: Domain Specific Language for Parallel Real-Time Stream Processing

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DSPE: Domain Specific Language for Parallel Real-Time Stream Processing

Chat with Graph Search

Highly Parallel RTL Simulation

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Imaging sensor device using an array of single-photon avalanche diode photodetectors

Assessment framework for deepfake detection in real-world situations

EdgeAI-Aware Design of In-Memory Computing Architectures

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

The 2024 Magnonics Roadmap

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs

Exploring High-Performance and Energy-Efficient Architectures for Edge AI-Enabled Applications

Secure Interface Design Leveraging Hardware/Software Support

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

BiomedBench: A benchmark suite of TinyML biomedical applications for low-power wearables

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Post-Moore's Law Fusion: High-Bandwidth Memory, Accelerators, and Native Half-Precision Processing for CPU-Local Analytics

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles