STMBench7: A Benchmark for Software Transactional Memory

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STMBench7: A Benchmark for Software Transactional Memory

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Highly Parallel RTL Simulation

Transparent Multicore Scaling of Single-threaded Network Functions

EdgeAI-Aware Design of In-Memory Computing Architectures

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Automated Formal Verification of Software Network Functions

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

One-shot Garbage Collection for In-memory OLTP through Temporality-aware Version Storage

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

The splay-list: a distribution-adaptive concurrent skip-list

WarpAttack: Bypassing CFI through Compiler-Introduced Double-Fetches

Cooperative Concurrency Control for Write-Intensive Key-Value Workloads

Vision Transformer Adapters for Generalizable Multitask Learning

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Efficient Concurrent Analytical Query Processing using Data and Workload-conscious Sharing

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Chaosity: Understanding Contemporary NUMA-architectures

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs