Flexible hardware acceleration for instruction-grain program monitoring

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Neurodegenerative and neuroinflammatory disorders often involve complex pathophysiological mechanisms that are â to this date â only partially understood. A more comprehensive understanding of those microstructural processes and their characterization ...

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

The collimation system of the Future Circular Collider, operating with leptons (FCC-ee), must protect not only the experiments against backgrounds, but also the machine itself from beam losses. With a 17.8 MJ stored energy of the electron and positron beam ...

Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability and hardware-level parallelism. While FPGAs are typically used by one tenant at a time, multitenant schemes supporting spatial sharing of c ...

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

TimberSLAM (TSLAM) is an object-centered, tag-based visual self-localization and mapping (SLAM) system for monocular RGB cameras. It was specifically developed to support a robust and augmented reality pipeline for close-range, noisy, and cluttered fabrica ...

In algorithms for solving optimization problems constrained to a smooth manifold, retractions are a well-established tool to ensure that the iterates stay on the manifold. More recently, it has been demonstrated that retractions are a useful concept for ot ...

Motivated by the transfer of proofs between proof systems, and in particular from first order automated theorem provers (ATPs) to interactive theorem provers (ITPs), we specify an extension of the TPTP derivation text format to describe proofs in first-ord ...

Volume electron microscopy is the method of choice for the in situ interrogation of cellular ultrastructure at the nanometer scale, and with the increase in large raw image datasets generated, improving computational strategies for image segmentation and s ...

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

Dataflow programming is a methodology that enables the development of high-level, parametric programs that are independent of the underlying platform. This approach is particularly useful for heterogeneous platforms, as it eliminates the need to rewrite ap ...

Native reactive electrophilic species (RES) are long-recognized regulators of pathophysiology; yet, knowledge surrounding how RES regulate context-specific biology remains limited. The latest technological advances in profiling and precision decoding of RE ...

Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The lat ...

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

Modern data management systems aim to provide both cutting-edge functionality and hardware efficiency. With the advent of AI-driven data processing and the post-Moore Law era, traditional memory-bound scale-up data management operations face scalability ch ...

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

Accessing input data is a critical operation in data analytics: i) slow data access significantly degrades performance, and ii) storing everything in the fastest medium, i.e., memory, incurs high operational and hardware costs. Further, while GPUs offer in ...

The opportunities provided by adopting digitally-generated visual tools in urban participatory planning are compelling. These visual tools can promote interactions between authorities and citizens and among citizens. However, the urban participatory practi ...

Energy efficiency is crucial for the sustainable operation of all industrial and urban sectors. However, practicing engineers have seldom access to open-source tools that can readily evaluate and compare scenarios in terms of energy consumption, cost, and ...

Flexible hardware acceleration for instruction-grain program monitoring

Chat with Graph Search

Development and clinical validation of computational imaging biomarkers for neurodegenerative diseases

EdgeAI-Aware Design of In-Memory Computing Architectures

Collimation simulations for the FCC-ee

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

Highly Parallel RTL Simulation

TSLAM: a tag-based object-centered monocular navigation system for augmented manual woodworking

From low-rank retractions to dynamical low-rank approximation and back

SC-TPTP: An Extension of the TPTP Derivation Format for Sequent-Based Calculus

Modular segmentation, spatial analysis and visualization of volume electron microscopy datasets

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Structural Insights into Electrophiles and Electrophilic Metabolites Sensing and Signaling: The Missing Information

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Chaosity: Understanding Contemporary NUMA-architectures

Post-Moore's Law Fusion: High-Bandwidth Memory, Accelerators, and Native Half-Precision Processing for CPU-Local Analytics

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Media Coverage of 3D Visual Tools Used in Urban Participatory Planning

ROSMOSE: A Web-based Optimization Tool to Aid Decision-making for the Design and Operation of Industrial and Urban Energy Systems