Publications related to Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

Related publications (30)

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

FedSSA: Semantic Similarity-based Aggregation for Efficient Model-Heterogeneous Personalized Federated Learning

Zhuan Shi, Gang Wang

Federated learning (FL) is a privacy-preserving collaboratively machine learning paradigm. Traditional FL requires all data owners (a.k.a. FL clients) to train the same local model. This design is not well-suited for scenarios involving data and/or system ...

IJCAI2024

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

High-Level Synthesis of Dynamically Scheduled Circuits

Lana Josipovic

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

EPFL2021

Universally Scalable Concurrent Data Structures

Tudor Alexandru David

The increase in the number of cores in processors has been an important trend over the past decade. In order to be able to efficiently use such architectures, modern software must be scalable: performance should increase proportionally to the number of all ...

EPFL2017

Electronics Emulation for Real-Time Fault Location in Power Systems

François Pierre Gaugaz

This research presents a high-speed hardware platform dedicated to emulate electrical power networks for the fault location. The solution implements an algorithm based on the Electromagnetic Time-Reversal (EMTR) principle, which allows locating faults in v ...

EPFL2017

Efficient Multi-Word Compare and Swap

Rachid Guerraoui, Mihail Igor Zablotchi

Atomic lock-free multi-word compare-and-swap (MCAS) is a powerful tool for designing concurrent algorithms. Yet, its widespread usage has been limited because lock-free implementations of MCAS make heavy use of expensive compare-and-swap (CAS) instructions ...

Schloss Dagstuhl, Leibniz-Zentrum2020

Distributed Computing with Modern Shared Memory

Mihail Igor Zablotchi

In this thesis, we revisit classic problems in shared-memory distributed computing through the lenses of (1) emerging hardware technologies and (2) changing requirements. Our contributions consist, on the one hand, in providing a better understanding of th ...

EPFL2020

Efficient Adaptive Hard Real-time Multi-processor Systems

Stefanos Skalistis

Modern computing systems are based on multi-processor systems, i.e. multiple cores on the same chip. Hard real-time systems are required to perform particular tasks within certain amount of time; failure to do so characterises an unaccepted behavior. Hard ...

EPFL2017

Task scheduling for highly concurrent analytical and transaction workloads

Anastasia Ailamaki, Iraklis Psaroudakis

Systems and method for a task scheduler with dynamic adjustment of concurrency levels and task granularity are disclosed for improved execution of highly concurrent analytical and transactional systems. The task scheduler can avoid both over commitment and ...

2020

Efficient Protocols for Enforcing Causal Consistency in Geo-Replicated Key-Value Data Stores

Kristina Spirovska

Modern large-scale data platforms manage colossal amount of data, generated by the ever-increasing number of concurrent users. Geo-replicated and sharded key-value data stores play a central role when building such platforms. As the strongest consistency m ...

EPFL2020

MOOLs for MOOCs: A first edX scalable implementation

Denis Gillet, Christophe Salzmann, Yves Henri Philippe Piguet

Deploying remote laboratories at a large scale is the next challenge in remote experimentation. It is referred as Massive Open Online Labs (MOOLs). Being able to sustain a massive number of users accessing a specific resource concurrently is a complex task ...

IEEE2016

Optimistic Concurrency with OPTIK

Rachid Guerraoui, Vasileios Trigonakis

We introduce OPTIK, a new practical design pattern for designing and implementing fast and scalable concurrent data structures. OPTIK relies on the commonly-used technique of version numbers for detecting conflicting concurrent operations. We show how to i ...

ACM Press2016

Fast and Robust Memory Reclamation for Concurrent Data Structures

Rachid Guerraoui, Mihail Igor Zablotchi, Oana Maria Balmau

In concurrent systems without automatic garbage collection, it is challenging to determine when it is safe to reclaim memory, especially for lock-free data structures. Existing concurrent memory reclamation schemes are either fast but do not tolerate proce ...

2016

Lock-Unlock: Is That All? A Pragmatic Analysis of Locking in Software Systems

Rachid Guerraoui, Vasileios Trigonakis

A plethora of optimized mutex lock algorithms have been designed over the past 25 years to mitigate performance bottlenecks related to critical sections and locks. Unfortunately, there is currently no broad study of the behavior of these optimized lock alg ...

2019

Locking Made Easy

Rachid Guerraoui, Vasileios Trigonakis, Georgios Chatzopoulos

A priori, locking seems easy: To protect shared data from concurrent accesses, it is sufficient to lock before accessing the data and unlock after. Nevertheless, making locking efficient requires fine-tuning (a) the granularity of locks and (b) the locking ...

ACM Press2016

OneFile: A Wait-free Persistent Transactional Memory

Nachshon Cohen

A persistent transactional memory (PTM) library provides an easy-to-use interface to programmers for using byte-addressable non-volatile memory (NVM). Previously proposed PTMs have, so far, been blocking. We present OneFile, the first wait-free PTM with in ...

IEEE COMPUTER SOC2019

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Jeremy Hugues-Felix Constantin, Thomas Christoph Müller, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Speculative Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract pa ...

ASSOC COMPUTING MACHINERY2019

Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The analysis of the trace graphs generated by dataflow program executions has been shown to be an effective tool for exploring and optimizing the design space of application programs on manycore/multicore platforms. In this work a new approach aiming at fi ...

Springer2015