Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

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Atomic lock-free multi-word compare-and-swap (MCAS) is a powerful tool for designing concurrent algorithms. Yet, its widespread usage has been limited because lock-free implementations of MCAS make heavy use of expensive compare-and-swap (CAS) instructions ...

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Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

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Highly Parallel RTL Simulation

FedSSA: Semantic Similarity-based Aggregation for Efficient Model-Heterogeneous Personalized Federated Learning

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

High-Level Synthesis of Dynamically Scheduled Circuits

Universally Scalable Concurrent Data Structures

Electronics Emulation for Real-Time Fault Location in Power Systems

Efficient Multi-Word Compare and Swap

Distributed Computing with Modern Shared Memory

Efficient Adaptive Hard Real-time Multi-processor Systems

Task scheduling for highly concurrent analytical and transaction workloads

Efficient Protocols for Enforcing Causal Consistency in Geo-Replicated Key-Value Data Stores

MOOLs for MOOCs: A first edX scalable implementation

Optimistic Concurrency with OPTIK

Fast and Robust Memory Reclamation for Concurrent Data Structures

Lock-Unlock: Is That All? A Pragmatic Analysis of Locking in Software Systems

Locking Made Easy

OneFile: A Wait-free Persistent Transactional Memory

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Speculative Dataflow Circuits

Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies