Publications related to Size-aware Sharding For Improving Tail Latencies in In-memory Key-value Stores

Related publications (26)

Bodily self-consciousness as a framework to link sensory information and self-related components of episodic memory: behavioral, neuroimaging, and clinical evidence

The recollection of sensory information and subjective experience related to a personal past event depends on our episodic memory (EM). At the neural level, EM retrieval is linked with the reinstatement of hippocampal activity thought to recollect the sens ...

EPFL2023

SecureCells: A Secure Compartmentalized Architecture

Andrés Sánchez Marín, Babak Falsafi, Mathias Josef Payer, Siddharth Gupta, Atri Bhattacharyya, Yuanlong Li, Florian Hofhammer

Modern programs are monolithic, combining code of varied provenance without isolation, all the while running on network-connected devices. A vulnerability in any component may compromise code and data of all other components. Compartmentalization separates ...

2023

How to Achieve Large-Area Ultra-Fast Operation of MoS 2 Monolayer Flash Memories?

Asmund Kjellegaard Ottesen, Aleksandra Radenovic, Andras Kis, Zhenyu Wang, Yanfei Zhao, Mukesh Kumar Tripathi, Guilherme Migliato Marega, Hyungoo Ji

Memory devices have returned to the spotlight due to increasing interest in using in-memory computing architectures to make data-driven algorithms more energy-efficient. One of the main advantages of this architecture is the efficient performance of vector ...

2023

Engram cell connectivity as a mechanism for information encoding and memory function

Maurizio Ferdinando Pezzoli

Information derived from experiences is incorporated into the brain as changes to ensembles of cells, termed engram cells, which allow memory storage and recall. The mechanism by which those changes hold specific information is unclear. Here, we test the h ...

Cell Press2023

Cooperative Concurrency Control for Write-Intensive Key-Value Workloads

Babak Falsafi, Alexandros Daglis, Mark Johnathon Sutherland

Key-Value Stores (KVS) are foundational infrastructure components for online services. Due to their latency-critical nature, today’s best-performing KVS contain a plethora of full-stack optimizations commonly targeting read-mostly, popularity-skewed worklo ...

ACM2023

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Guilherme Migliato Marega

Machine learning and data processing algorithms have been thriving in finding ways of processing and classifying information by exploiting the hidden trends of large datasets. Although these emerging computational methods have become successful in today's ...

EPFL2023

Rebooting Virtual Memory with Midgard

Siddharth Gupta

Virtual Memory (VM) is a critical programming abstraction that is widely used in various modern computing platforms. With the rise of datacenter computing and birth of planet-scale online services, the semantic and capacity requirements from memory have ev ...

EPFL2023

Modulation of working memory duration by synaptic and astrocytic mechanisms

Sophia Becker

Short-term synaptic plasticity and modulations of the presynaptic vesicle release rate are key components of many working memory models. At the same time, an increasing number of studies suggests a potential role of astrocytes in modulating higher cognitiv ...

PUBLIC LIBRARY SCIENCE2022

Where does the engram come from? Study of prefrontal cortex inputs during memory consolidation

Lucie Pauline Dixsaut

The formation and storage of memories has been under deep investigation for several decades. Nevertheless, the precise contribution of each brain region involved in this process and the interplay between them across memory consolidation is still largely de ...

EPFL2022

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Robert Giterman

Side-channel attacks constitute a concrete threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with 6T SRAM macrocells often dominate the area and power consumption of these SoCs. Regardless of the computational platform, the side-channel ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Paolo Ienne, Mikhail Asiatici

Efficient large-scale graph processing is crucial to many disciplines. Yet, while graph algorithms naturally expose massive parallelism opportunities, their performance is limited by the memory system because of irregular memory accesses. State-of-the-art ...

IEEE COMPUTER SOC2021

Engram cell connectivity: an evolving substrate for information storage

Maurizio Ferdinando Pezzoli

Understanding memory requires an explanation for how information can be stored in the brain in a stable state. The change in the brain that accounts for a given memory is referred to as an engram. In recent years, the term engram has been operationalized a ...

CURRENT BIOLOGY LTD2021

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Mikhail Asiatici

Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

EPFL2021

The influence of anodal transcranial direct current stimulation over the right auditory cortex on interference effects in memory for melodies

Steffen Alexander Herff

The study investigates how transcranial direct current stimulation (tDCS) over the auditory cortex (AC) modulates memory for melodies under different noise conditions, whilst also considering cumulative disruptive interference effects. Forty-one participan ...

ACADEMIC PRESS INC ELSEVIER SCIENCE2021

Rethinking Software Runtimes for Disaggregated Memory

Sanidhya Kashyap

Disaggregated memory can address resource provisioning inefficiencies in current datacenters. Multiple software runtimes for disaggregated memory have been proposed in an attempt to make disaggregated memory practical. These systems rely on the virtual mem ...

ASSOC COMPUTING MACHINERY2021

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA

Paolo Ienne, Mikhail Asiatici, Gabor Andras Csordas

For efficient acceleration on FPGA, it is essential for external memory to match the throughput of the processing pipelines. However, the usable DRAM bandwidth decreases significantly if the access pattern causes frequent row conflicts. Memory controllers ...

IEEE COMPUTER SOC2019

Mitigating Load Imbalance in Distributed Data Serving with Rack-Scale Memory Pooling

Babak Falsafi, Edouard Bugnion, Boris Robert Grot, Alexandros Daglis, Stanko Novakovic, Dmitrii Ustiugov

To provide low-latency and high-throughput guarantees, most large key-value stores keep the data in the memory of many servers. Despite the natural parallelism across lookups, the load imbalance, introduced by heavy skew in the popularity distribution of k ...

2019

Underlying mechanisms of episodic autobiographical memory and self-consciousness

Lucie Bréchet

Cognitive neuroscience has been examining consciousness associated with the subject, that is the self of the conscious experience and its related multisensory processing of bodily signals, the so-called bodily self-consciousness. Different line of research ...

EPFL2019

Collective Memory and Resistance: Visual explorations in the Historic Centre and Films of Mexico City

Lesslie Astrid Herrera Quiroz

Today, institutionalised discourses surrounding heritage have social and physical impacts, with the potential to lead to a break between inhabitants' collective memory of popular neighbourhoods, and their transforming territories. In this context, the acti ...

EPFL2019

Rack-Scale Memory Pooling for Datacenters

Stanko Novakovic

The rise of web-scale services has led to a staggering growth in user data on the Internet. To transform such a vast raw data into valuable information for the user and provide quality assurances, it is important to minimize access latency and enable in-me ...

EPFL2017