Performance Analysis of 3-D Monolithic Integrated Circuits

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Wafer scale nanostencil lithography is used to define 200 nm scale mechanically resonating silicon cantilevers monolithically integrated into CMOS circuits. We demonstrate the simultaneous patterning of ~2000 nanodevices by post-processing standard CMOS wafers using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies around 1.5 MHz were measured in air and vacuum and tuned by applying dc voltages of 10V and 1V respectively.

Micro-Hall sensors made of Bi have been previously fabricated and have shown interesting properties for magnetic field detection. In this project, new ideas to improve the performance of these Hall sensors and to explore ferromagnetic metals are developed. Ni and Bi protected with Al2O3 are used as materials to realize the sensing element. Different thicknesses between 10 and 100 nm of Ni and Bi are deposited by evaporation and structured with lift-off. The electrodes are made of Ti/Al. A Pt thin film is de

We study the electronic structure and the dielectric permittivity of ultrathin oxide layers on Si(I 00) substrates. By considering two different Si(l 00)-SiO2 interface models, we first show that the electronic structure in the interfacial oxide differs from the corresponding bulk counterpart due to silicon-induced gap states. Then, we calculate the permittivity of the first few angstroms of the oxide within a density-functional approach. For sub-nanometric oxides, we find that the oxide permittivity increa

We give a short survey of several techniques to construct codes on GF(q) that approach the capacity of the q-ary symmetric channel. The q-ary symmetric channel represents the next level of difficulty after the binary erasure channel (BEC). Since the channel is more complex than the BEC, one may hope that codes and decoding algorithms that approach the capacity of this channel for large q may be modified to yield capacity-approaching codes for smaller values of q as well.

Fingerprinting summarizes the history of internal processor state updates into a cryptographic signature. The processors in a dual modular redundant pair periodically exchange and compare fingerprints to corroborate each other's correctness. relative to other techniques, fingerprinting offers superior error coverage and significantly reduces the error-detection latency and bandwidth.

This paper addresses the problem of optimal channel rate allocation for media streaming in active networks, where intermediate nodes are able to perform basic FEC decoding/encoding operations. FEC performance is analyzed in the case of hop-by-hop FEC protection, and compared with an end-to-end FEC scenario, in order to demonstrate the benefits of FEC operations in the intermediate nodes. An optimization problem is formulated, based on a distortion model for video streaming over lossy channels. Finally, the

The current repartition inside a HTS cable is very important for determining its AC losses and can be influenced by the uniformity of several parameters, either linked to the physical properties of the individual tapes (critical current Ic and power index n) or due to the manufacturing process (contact resistance). This work investigates the importance of the non-uniformity of these parameters for a manufactured 16-tape straight superconducting cable by means of finite element method (FEM) simulations. The

A two-dimensional (2-D) array (4 by 8) of single-photon avalanche diodes integrated in an industrial complementary metal-oxide-semiconductor (CMOS) process is presented. Each pixel combines a photodiode biased above its breakdown voltage in the so-called Geiger mode, a quenching resistor, and a simple comparator. The pitch between the pixels is 75 mum and the diameter of each pixel is 6.4 mum. The full integration allows reducing the number of charge carriers in a Geiger pulse. The electroluminescence respo

Tuning and high frequency capabilities and dynamic range performance of continuous-time oscillators and filters, using the weak inversion operation mode of a low-cost conventional 0.5 μm CMOS technology and multi-tanh linearisation technique are examined. Experimental results in the 1.6 to 19 MHz tuning range are reported.

Sequence recognition performance is often summarised first in terms of the number of hits (H), substitutions (S), deletions (D) and insertions (I), and then as a single statistic by the "word error rate" WER = 100(S D I)/(H S D). While in common use, WER has two disadvantages as a performance measure. One is that it has no upper bound, so it doesn't tell you how good a system is, only that one is better than another. The other is that it is not D/I symmetric, although deletions and insertions are equally di

From a shape change point of view, the shape memory effect is not intrinsically reversible. Therefore developing Shape Memory Alloys (SMA) actuators, i.e. devices producing a motion, requires a suitable method to bypass this intrinsic property. Since the shape memory effect discovery, different methods, either intrinsic like the «Two-Way Shape Memory Effect » or extrinsic like the use of a biasing element have been investigated. In this paper, a new method based on a local annealing of the material is prese

An electronic compass made of a new planar 2D micro-fluxgate sensor is presented. The magnetometer is integrated in a standard CMOS process, and uses a post-processed cross shape ferromagnetic amorphous core. This core is diagonally placed above a single square excitation coil common to both measurement axes. The silicon chip includes the driving and readout electronics, the excitation and pick-up coils made of the two CMOS process metallization layers. The ferromagnetic core is integrated from commercially

Performance Analysis of 3-D Monolithic Integrated Circuits

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Full wafer integration of NEMS on CMOS by nanostencil lithography

MICRO-HALL SENSORS ON SU-8 CANTILEVERS FOR MAGNETIC IMAGINIG

Electronic and dielectric properties of a suboxide interlayer at the silicon-oxide interface in MOS devices

Capacity-approaching codes on the q-ary symmetric channel for large q

Fingerprinting: Bounding the Soft-Error Detection Latency and Bandwidth

Optimal FEC Rate for Media Streaming in Active Networks

Numerical modelling of a HTS cable in AC regime

First fully integrated 2-D array of single-photon detectors in standard CMOS technology

Continuous-time CMOS circuits based on multi-tanh linearisation principle

An information theoretic measure of sequence recognition performance

Laser annealing of shape memory alloys : A versatile tool for developing smart micro-devices

CMOS planar 2D micro-fluxgate sensor