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In this paper, the influence of temperature and back-gate bias is experimentally investigated on 22 nm FDSOI CMOS process. Cryogenic DC characterization was carried out under various back-gate voltages, V back , from 2.95 K back to 300 K. An abrupt drop-of ...
In this letter, we present a multi-channel in-plane-gate field effect transistor (MC-IPGFET). In the proposed device, multiple vertically stacked two-dimensional electron gases (2DEGs) are simultaneously controlled by lateral in-plane gates formed with the ...
Institute of Electrical and Electronics Engineers2020
We have used scanning photocurrent microscopy to explore the electronic characteristics of a graphene p-n junction fabricated by local chemical doping of a graphene sheet. The photocurrent signal at the junction was found to be most prominent for gate volt ...
