Toward Predictable Performance in Software Packet-Processing Platforms

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Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

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The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

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Computer systems rely heavily on abstraction to manage the exponential growth of complexity across hardware and software. Due to practical considerations of compatibility between components of these complex systems across generations, developers have favou ...

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...

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The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the use ...

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The lat ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

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Accessing input data is a critical operation in data analytics: i) slow data access significantly degrades performance, and ii) storing everything in the fastest medium, i.e., memory, incurs high operational and hardware costs. Further, while GPUs offer in ...

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Dataflow programming is a methodology that enables the development of high-level, parametric programs that are independent of the underlying platform. This approach is particularly useful for heterogeneous platforms, as it eliminates the need to rewrite ap ...

In 1948, Claude Shannon laid the foundations of information theory, which grew out of a study to find the ultimate limits of source compression, and of reliable communication. Since then, information theory has proved itself not only as a quest to find the ...

Finding cycles in directed graphs enables important applications in various domains such as finance, biology, chemistry, and network science. However, as the size of graph datasets continues to grow, it becomes increasingly difficult to discover cycles wit ...

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

Toward Predictable Performance in Software Packet-Processing Platforms

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Highly Parallel RTL Simulation

EdgeAI-Aware Design of In-Memory Computing Architectures

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Imaging sensor device using an array of single-photon avalanche diode photodetectors

Secure Interface Design Leveraging Hardware/Software Support

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Oligolithic Cross-task Optimizations across Isolated Workloads

Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Post-Moore's Law Fusion: High-Bandwidth Memory, Accelerators, and Native Half-Precision Processing for CPU-Local Analytics

Chaosity: Understanding Contemporary NUMA-architectures

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Time vs. Truth: Age-Distortion Tradeoffs and Strategies for Distributed Inference

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference