Publications related to A Novel Conflict-Free Memory and Processor Architecture for DVB-T2 LDPC Decoding

Related publications (33)

EdgeAI-Aware Design of In-Memory Computing Architectures

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Secure Interface Design Leveraging Hardware/Software Support

Atri Bhattacharyya

Computer systems rely heavily on abstraction to manage the exponential growth of complexity across hardware and software. Due to practical considerations of compatibility between components of these complex systems across generations, developers have favou ...

EPFL2024

A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yifei Shen, Yuqing Ren, Hassan Harb

5G New Radio (NR) has stringent demands on both performance and complexity for the design of low-density parity-check (LDPC) decoding algorithms and corresponding VLSI implementations. Furthermore, decoders must fully support the wide range of all 5G NR bl ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Highly Parallel RTL Simulation

Seyedmahyar Emami

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Optimizing Polar Codes for Reduced Latency Successive Cancellation List Decoder

Yuqing Ren

This paper presents the application of genetic algorithms (GenAlg) to optimize polar codes for reducing the decoding latency of fast cyclic redundancy check aided successive cancellation list decoders. The theoretical decoding time steps (TS) in code const ...

2024

On Speed and Advantage : Results in Information Velocity and Monitoring Problems

Reka Inovan

Information theory has allowed us to determine the fundamental limit of various communication and algorithmic problems, e.g., the channel coding problem, the compression problem, and the hypothesis testing problem. In this work, we revisit the assumptions ...

EPFL2024

Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

Qunyou Liu, David Atienza Alonso, Marina Zapater Sancho, Darong Huang, Luis Maria Costero Valero

The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the use ...

2024

An aircraft assembly process formalism and verification method based on semantic modeling and MBSE

Dimitrios Kyritsis, Jinzhi Lu, Xiaochen Zheng

The aircraft assembly system is highly complex involving different stakeholders from multiple domains. The design of such a system requires comprehensive consideration of various industrial scenarios aiming to optimize key performance indicators. Tradition ...

Elsevier Sci Ltd2024

Exploring High-Performance and Energy-Efficient Architectures for Edge AI-Enabled Applications

Joshua Alexander Harrison Klein

The desire and ability to place AI-enabled applications on the edge has grown significantly in recent years. However, the compute-, area-, and power-constrained nature of edge devices are stressed by the needs of the AI-enabled applications, due to a gener ...

EPFL2024

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi

The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

2024

Bridging Monte Carlo worlds: a new framework for accelerator simulations applied on shielding and machine protection studies

André Donadon Servelle

This thesis delves into the critical study of particle transport in matter, particularly emphasising its implications for machine protection at CERN's accelerator complex and facilities. To conduct studies of this nature, FLUKA and Geant4 stand out within ...

EPFL2024

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Adam Shmuel Teman, Robert Giterman

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...

MDPI2024

Towards Scalable Electronics: Synthetic 2D Materials for Large-Area 2D Circuit Integration

Zhenyu Wang

In the past decades, a significant increase of the transistor density on a chip has led to exponential growth in computational power driven by Moore's law. To overcome the bottleneck of traditional von-Neumann architecture in computational efficiency, effo ...

EPFL2024

Spatial Modeling for Building Design Evaluation: from Visual Landscape Quality Assessment to Devaluation Risk Estimation

Adam Robert Swietek

Zoning reform is a crucial tool for cities to adapt to contemporary challenges. However, its implementation remains challenging. Property owners, with a vested interest in the value of their neighborhoods, are sensitive to local developments and the potent ...

EPFL2024

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Guilherme Migliato Marega

Machine learning and data processing algorithms have been thriving in finding ways of processing and classifying information by exploiting the hidden trends of large datasets. Although these emerging computational methods have become successful in today's ...

EPFL2023

Rebooting Virtual Memory with Midgard

Siddharth Gupta

Virtual Memory (VM) is a critical programming abstraction that is widely used in various modern computing platforms. With the rise of datacenter computing and birth of planet-scale online services, the semantic and capacity requirements from memory have ev ...

EPFL2023

Chaosity: Understanding Contemporary NUMA-architectures

Andreea Nica, Anastasia Ailamaki, Viktor Sanca, Syed Mohammad Aunn Raza, Hamish Mcniece Hill Nicholson

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

2023

Low Power LDPC Decoding by Reliable Voltage Down-Scaling

Andreas Peter Burg

Low-Density Parity-Check (LDPC) decoder is among the power hungry building blocks of wireless communication systems. Voltage scaling down to Near-Threshold (NT) voltages substantially improves energy efficiency, in theory up 10x. However, tuning the voltag ...

IEEE2023

How to Achieve Large-Area Ultra-Fast Operation of MoS 2 Monolayer Flash Memories?

Asmund Kjellegaard Ottesen, Aleksandra Radenovic, Andras Kis, Zhenyu Wang, Yanfei Zhao, Mukesh Kumar Tripathi, Guilherme Migliato Marega, Hyungoo Ji

Memory devices have returned to the spotlight due to increasing interest in using in-memory computing architectures to make data-driven algorithms more energy-efficient. One of the main advantages of this architecture is the efficient performance of vector ...

2023

Analysis of the influence of errors in DNA-based image coding

Touradj Ebrahimi, Michela Testolina, Davi Nachtigall Lazzarotto

In the last decade, DNA has been increasingly investigated as an alternative medium for cold data storage, presenting several advantages over standard hard drives such as a higher density, longer lifespan and lower energy consumption. However, such coding ...

2023