Publication
This paper presents a charge controlling circuit technique to integrate a charge balancer circuitry in the output-stage of electrical neural stimulators with the aim to reduce the area and the power consumption of the charge balancing circuitry. The proposed architecture is an inter-pulse charge control technique that senses the electrode voltage and provides stable charge balancing throughout the entire stimulation parameters. To ensure the stability, only one side of the output stage is active during the charge balancing phase. The stimulator employed in the proposed system has an adaptive quad-rail compliance as high as 45 V, configurable from 5 to 45 V, according to the requirement of the application. Thanks to a straightforward structure of the proposed charge control circuit, the proposed charge balancer (CB) performs with low power consumption (from 3.5 to 14.8 mu W), occupies small silicon area (0.102 mm(2)), and has a high dynamic-range of power supply compliance in comparison to similar existing consequence-based charge control blocks as well as performs charge balancing for a wider range of tissue impedance. According to its reported characteristics, the proposed method leads to an improvement in stability, power consumption, area and power supply compliance as well as tissue impedance range compared to the state-of-the-art charge balancing methods.