Publication

Practical Exact Synthesis

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, Eleonora Testa, Winston Jason Haaswijk
2018
Conference Papers

Abstract

In this paper, we discuss recent advances in exact synthesis, considering both their efficient implementation and various applications in which they can he employed. We emphasize on solving exact synthesis through Boolean satisfiability (SAT) encodings. Different SAT encodings for exact synthesis are compared, and examined the applications to multi-level logic synthesis, in both area and depth optimization. Another application of SAT based exact synthesis is optimization under many constraints. These constraints can, e.g., be a fixed fanout or delay constraints. Finally, we end our discussion by proposing directions for future research in exact synthesis.

Official source

https://infoscience.epfl.ch/entities/publication/5b9e4655-4a03-443a-8d11-17e79ff668c6

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Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, Eleonora Testa, Winston Jason Haaswijk
2018
Conference Papers

Abstract

Official source

https://infoscience.epfl.ch/entities/publication/5b9e4655-4a03-443a-8d11-17e79ff668c6

About this result

Related concepts (24)

Logic optimization

Logic optimization is a process of finding an equivalent representation of the specified logic circuit under one or more specified constraints. This process is a part of a logic synthesis applied in digital electronics and integrated circuit design. Generally, the circuit is constrained to a minimum chip area meeting a predefined response delay. The goal of logic optimization of a given circuit is to obtain the smallest logic circuit that evaluates to the same values as the original one.

Logic synthesis

In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer program called a synthesis tool. Common examples of this process include synthesis of designs specified in hardware description languages, including VHDL and Verilog. Some synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs.

Espresso heuristic logic minimizer

The ESPRESSO logic minimizer is a computer program using heuristic and specific algorithms for efficiently reducing the complexity of digital logic gate circuits. ESPRESSO-I was originally developed at IBM by Robert K. Brayton et al. in 1982. and improved as ESPRESSO-II in 1984. Richard L. Rudell later published the variant ESPRESSO-MV in 1986 and ESPRESSO-EXACT in 1987. Espresso has inspired many derivatives. Electronic devices are composed of numerous blocks of digital circuits, the combination of which performs the required task.

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Practical Exact Synthesis

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