Publications related to Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Related publications (33)

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

EdgeAI-Aware Design of In-Memory Computing Architectures

Marco Antonio Rios

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi

The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

2024

Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware

Anna Burdina, David Atienza Alonso, Giovanni Ansaloni, Miguel Peon Quiros, Pasquale Davide Schiavone

In the past decade, computing systems have significantly increased in complexity and power consumption. Nowadays, heterogeneous multi-processor systems-on-chip (MPSoCs) integrate many computing cores. Heterogeneous MPSoCs often comprise general-purpose pro ...

Association for Computing Machinery, Inc2024

Is the powersave governor really saving power?

David Atienza Alonso, Darong Huang, Luis Maria Costero Valero

A frequency scaling governor is critical for the performance management of cloud servers, as it enhances energy efficiency and helps to control operational temperatures, thereby ensuring system reliability. However, our in-depth analysis of the application ...

2024

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mathias Josef Payer, Mirjana Stojilovic, Ognjen Glamocanin, Shashwat Shrivastava

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

Programmable Seizure Detector Using a 32-bit RISC Processor for Implantable Medical Devices

Alexandre Schmid, Keyvan Farhang Razi

A programmable patient-customized epileptic seizure detector is proposed in this paper to enable neurologists and patients to have constructive interactions with the implantable medical device. The programmability feature is enabled by designing a low-powe ...

IEEE2023

Rebooting Virtual Memory with Midgard

Siddharth Gupta

Virtual Memory (VM) is a critical programming abstraction that is widely used in various modern computing platforms. With the rise of datacenter computing and birth of planet-scale online services, the semantic and capacity requirements from memory have ev ...

EPFL2023

Low Power LDPC Decoding by Reliable Voltage Down-Scaling

Andreas Peter Burg

Low-Density Parity-Check (LDPC) decoder is among the power hungry building blocks of wireless communication systems. Voltage scaling down to Near-Threshold (NT) voltages substantially improves energy efficiency, in theory up 10x. However, tuning the voltag ...

IEEE2023

Imprecise Store Exceptions

Babak Falsafi, Mathias Josef Payer, Siddharth Gupta, Yunho Oh, Yuanlong Li, Abhishek Bhattacharjee, Qingxuan Kang

Precise exceptions are a cornerstone of modern computing as they provide the abstraction of sequential instruction execution to programmers while accommodating microarchitectural optimizations. However, increasing compute capabilities in deep memory hierar ...

ACM2023

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Aurélien François Gilbert Bloch

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

EPFL2023

Digital One-Shot Charge-balancing Method for Implantable Current-Mode Electrical Stimulation

Alexandre Schmid, Keyvan Farhang Razi

A low-power digital charge balancing system, which ensures the safe operation of constant-current biphasic stimulation is presented. The concept of the proposed charge-balancing technique is to utilize a hybrid method consisting of anodic pulse modulation ...

IEEE2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

A Delay and Power Efficient Voltage Level Shifter with Low Leakage Power

Alexandre Schmid, Mehdi Saberi

This paper presents a new power-efficient and high-speed voltage level shifter. In the proposed structure, the existing contentions at the internal nodes are reduced using auxiliary transistors and feedback networks, leading to a significant reduction in t ...

IEEE2023

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Ognjen Glamocanin

The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...

EPFL2023

Chaosity: Understanding Contemporary NUMA-architectures

Andreea Nica, Anastasia Ailamaki, Viktor Sanca, Syed Mohammad Aunn Raza, Hamish Mcniece Hill Nicholson

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

2023

SecureCells: A Secure Compartmentalized Architecture

Andrés Sánchez Marín, Babak Falsafi, Mathias Josef Payer, Siddharth Gupta, Atri Bhattacharyya, Yuanlong Li, Florian Hofhammer

Modern programs are monolithic, combining code of varied provenance without isolation, all the while running on network-connected devices. A vulnerability in any component may compromise code and data of all other components. Compartmentalization separates ...

2023

Front-End Circuits for Radiation-Hard Monolithic CMOS Sensors targeting High-Energy Physics Applications

Francesco Piro

Monolithic pixel sensors integrate the sensor matrix and readout in the same silicon die, and therefore present several advantages over the more largely used hybrid detectors in high-energy physics. They offer an easier detector assembly, lower cost, lower ...

EPFL2023

System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms

David Atienza Alonso, Giovanni Ansaloni, Marina Zapater Sancho, Joshua Alexander Harrison Klein, Rafael Medina Morillas

Multi-Chiplet architectures are being increasingly adopted to support the design of very large systems in a single package, facilitating the integration of heterogeneous components and improving manufacturing yield. However, chiplet-based solutions have to ...

2023

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Benoît Walter Denkinger

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

EPFL2023