SPAD Developed in 55 nm Bipolar-CMOS-DMOS Technology Achieving Near 90% Peak PDP

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In this article, we present 10 mu m diameter SPADs fabricated in 110 nm CIS technology based on an N (+) /HVPW junction, with enhanced sensitivity at short wavelengths. To reduce tunneling noise due to the highly-doped layers in the process, a doping compe ...

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SPAD Developed in 55 nm Bipolar-CMOS-DMOS Technology Achieving Near 90% Peak PDP

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A 73% Peak PDP Single-Photon Avalanche Diode Implemented in 110 nm CIS Technology With Doping Compensation

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