Scalable instruction set simulator for thousand-core architectures running on GPGPUs

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Scalable instruction set simulator for thousand-core architectures running on GPGPUs

Chat with Graph Search

LIONHEART: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles

Highly Parallel RTL Simulation

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD

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Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware

Surface-based GPU-friendly geometry modeling for detector simulation

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

EdgeAI-Aware Design of In-Memory Computing Architectures

CloudProphet: A Machine Learning-Based Performance Prediction for Public Clouds

Exploring High-Performance and Energy-Efficient Architectures for Edge AI-Enabled Applications

Spatial Modeling for Building Design Evaluation: from Visual Landscape Quality Assessment to Devaluation Risk Estimation

Assessment framework for deepfake detection in real-world situations

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Post-Moore's Law Fusion: High-Bandwidth Memory, Accelerators, and Native Half-Precision Processing for CPU-Local Analytics

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing