Publication

Scalable instruction set simulator for thousand-core architectures running on GPGPUs

David Atienza Alonso, Martino Ruggiero, Shivani Raghav
2010
Conference Papers

Abstract

Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms are not able to tackle the complexity issues introduced by 1000-core future scenarios. We present a fast and accurate simulation framework targeting extremely large parallel systems by specifically taking advantage of the inherent potential processing parallelism available in modern GPGPUs.

Official source

https://infoscience.epfl.ch/entities/publication/46703f64-35e5-4ef5-b4ed-c29c9029853c

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Scalable instruction set simulator for thousand-core architectures running on GPGPUs

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