Enhancing Channel Decoding Through Full-Custom Hardware Design

Forward error correction (FEC) codes are essential components of both wired and wireless communication systems. High-throughput decoding is necessary to meet the demands of modern communication links operating at multiple gigabits per second. However, these advanced algorithms are often complex and costly to implement in terms of power and area, which pushes the limits of the most advanced technology nodes. Traditionally, these demanding signal processing tasks are realized using semi-custom, synchronous design principles with hardware description languages (HDLs), synthesized through electronic design automation (EDA) tools. This conservative approach often cannot achieve the highest performance or the lowest power consumption. To address this challenge, we propose to use alternative circuit and design paradigms based on full-custom and mixed-signal techniques for critical blocks. We present sorters and parallel syndrome checks (SCs) as examples of such blocks that are used frequently in FEC.