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Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

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Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

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Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

FPGA-to-CPU Undervolting Attacks

Design and management of three-dimensional multi-processor systems-on-chip with integrated flow cell arrays

Optimization Methods for Control: From Embedded Programmable Hardware to Data-Driven Process Optimization

Fabrication and Characterization of High Aspect Ratio Amorphous Silicon Based Microchannel Plates

Improving First-Order Threshold Implementations of SKINNY

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Further Results on Efficient Implementations of Block Cipher Linear Layers

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs

JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

Collaborative Learning in the Jungle (Decentralized, Byzantine, Heterogeneous, Asynchronous and Nonconvex Learning)