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Method to manage the load of peripheral elements within a multicore system

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Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mathias Josef Payer, Mirjana Stojilovic, Ognjen Glamocanin, Shashwat Shrivastava

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

Reliable Microsecond-Scale Distributed Computing

Athanasios Xygkis

The landscape of computing is changing, thanks to the advent of modern networking equipment that allows machines to exchange information in as little as one microsecond. Such advancement has enabled microsecond-scale distributed computing, where entire dis ...

EPFL2023

Fundamental Limits in Statistical Learning Problems: Block Models and Neural Networks

Elisabetta Cornacchia

This thesis focuses on two selected learning problems: 1) statistical inference on graphs models, and, 2) gradient descent on neural networks, with the common objective of defining and analysing the measures that characterize the fundamental limits. In th ...

EPFL2023

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Dataflow programming is a methodology that enables the development of high-level, parametric programs that are independent of the underlying platform. This approach is particularly useful for heterogeneous platforms, as it eliminates the need to rewrite ap ...

SPRINGER2023

SecureCells: A Secure Compartmentalized Architecture

Andrés Sánchez Marín, Babak Falsafi, Mathias Josef Payer, Siddharth Gupta, Atri Bhattacharyya, Yuanlong Li, Florian Hofhammer

Modern programs are monolithic, combining code of varied provenance without isolation, all the while running on network-connected devices. A vulnerability in any component may compromise code and data of all other components. Compartmentalization separates ...

2023

Short-term dynamics of drainage density based on a combination of channel flow state surveys and water level measurements

Andrea Rinaldo, Jana Freiin von Freyberg, Izabela Bujak-Ozga

Headwater streams often experience intermittent flow. Consequently, the flowing drainage network expands and contracts and the flowing drainage density (DD) varies over time. Monitoring the DD dynamics is essential to understand the processes controlling i ...

Wiley2023

Estimating pollution spread in water networks as a Schrödinger bridge problem with partial information

Isabel Haasler

Incidents where water networks are contaminated with microorganisms or pollutants can result in a large number of infected or ill persons, and it is therefore important to quickly detect, localize and estimate the spread and source of the contamination. In ...

Elsevier2023

Automatic and high-precision microseismic monitoring of progressive failure prior, during, and after tunnel excavation

Brice Tanguy Alphonse Lecampion, Seyyedmaalek Momeni, Christophe Nussbaum

Acoustic emission (AE) monitoring is commonly used to inspect the health of a structure continuously. During fracture processes elastic waves of AE are created and emitted, and sensors can capture these waves. The acquired signals can be processed to track ...

2023

Computational Imaging SPAD Cameras

Andrei Ardelean

Vision systems built around conventional image sensors have to read, encode and transmit large quantities of pixel information, a majority of which is redundant. As a result, new computational imaging sensor architectures were developed to preprocess the r ...

EPFL2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Caching and Neutrality

Aikaterini Argyraki, Pavlos Nikolopoulos, Muhammad Abdullah

We are used to defining network neutrality as absence of traffic differentiation, like policing or shaping. These mechanisms, however, are often not what determines end-users’ quality of experience (QoE). Most content today is accessed through edge caches, ...

ACM Association for Computing Machinery2023

Equilibria in Network Constrained Energy Markets

Leonardo Massai

We study an energy market composed of producers who compete to supply energy to different markets and want to maximize their profits. The energy market is modeled by a graph representing a constrained power network where nodes represent the markets and lin ...

Elsevier2023

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Benoît Walter Denkinger

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

EPFL2023

Artificial Neural Network Training on an Optical Processor via Direct Feedback Alignment

Florent Gérard Krzakala

Artificial Neural Networks (ANN) are habitually trained via the back-propagation (BP) algorithm. This approach has been extremely successful: Current models like GPT-3 have O(10 11 ) parameters, are trained on O(10 11 ) words and produce awe-inspiring resu ...

IEEE2023

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Paolo Ienne, Kubilay Atasu, Jovan Blanusa

Cycles are one of the fundamental subgraph patterns and being able to enumerate them in graphs enables important applications in a wide variety of fields, including finance, biology, chemistry, and network science. However, to enable cycle enumeration in r ...

Assoc Computing Machinery2023