Inverse Gating for Low Energy Block Ciphers

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

SiliFish is an open-source desktop application tomodel and study zebrafish swimming. Here, we explain how to define the general parameters of the model, define cell populations, place them within the spinal cord, and define their projections. We explain ho ...

Capacitive micromachined ultrasonic transducers (CMUTs) are regarded as an attractive candidate in bio-applications such as imaging and molecule monitoring. However, the previous researches on biochemical sensing are mostly air-coupled application based on ...

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

In the last few years, the field of lightweight cryptography has seen an influx in the number of block ciphers and hash functions being proposed. In the past there have been numerous papers that have looked at circuit level implementation of block ciphers ...

Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused ...

Ion-sensitive field-effect transistors (ISFETs) form a high sensitivity and scalable class of sensors, compatible with advanced complementary metal-oxide semiconductor (CMOS) processes. Despite many previous demonstrations about their merits as low-power i ...

Decentralized training of deep learning models enables on-device learning over networks, as well as efficient scaling to large compute clusters. Experiments in earlier works reveal that, even in a data-center setup, decentralized training often suffers fro ...

The aim of this thesis is to implement, analyze and improve the selected low noise clock generation and distribution techniques for ADC implementations. The thesis is divided into two parts. The first part focuses on the sampling phase generation and distr ...

Most of the cryptographic protocols that we use frequently on the internet are designed in a fashion that they are not necessarily suitable to run in constrained environments. Applications that run on limited-battery, with low computational power, or area ...

We explore different aspects of the multi-stage fracturing process such as stress interaction between growing hydraulic fractures, perforation friction, as well as the wellbore flow dynamics using a specifically developed numerical solver. In particular, g ...

Quasi-static piezoelectric actuators are used in micro-robotics due to the small displacements they can achieve, and they have been proven to be suitable for Self-Sensing Actuation (SSA) applications. The morphology and material of an actuator, and therefo ...

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply dual-edge-triggered ...

Developing large arrays of single-photon avalanche diodes (SPADs) with on-chip time-correlated single-photon counting (TCSPC) capabilities continues to be a difficult task due to stringent silicon real estate constraints, high data rates and system complex ...

Nanowire Field Effect Transistors (FETs) with multiple independent gates around a silicon channel feature ultimate gate control and are regarded as promising candidates for next generation transistors. Being inherently more complex than conventional gate-a ...

The implementation of the AES encryption core by Moradi et al. at Eurocrypt 2011 is one of the smallest in terms of gate area. The circuit takes around 2400 gates and operates on an 8 bit datapath. However this is an encryption only core and unable to cate ...

Today's rapid advances in quantum computing hardware call for scalable synthesis methods to map combinational logic represented as multi-level Boolean networks (e.g., an and inverter graph, AIG) to quantum circuits. Such synthesis process must yield revers ...

In alpine skiing, intermediate times are usually measured with photocells. However, for practical reasons, the number of intermediate cells is limited to three⁻four, making a detailed timing analysis difficult. In this paper, we propose and validate a magn ...

Two models for the generation of self-oscillations of reed conical woodwinds are presented. The models use the fewest parameters (of either the resonator or the exciter), whose influence can be quickly explored. The formulation extends iterated maps obtain ...

The ability to control and pump high ionic strength fluids inside microchannels forms a major advantage for clinical diagnostics and drug screening processes, where high conductive biological and physiological buffers are used. Despite the known potential ...

Inverse Gating for Low Energy Block Ciphers

Chat with Graph Search

SiliFish: A desktop application to model swimming behavior in developing zebrafish (Danio rerio)

New Insights for Parasitic Effects of Label-Free Biosensors Based on Capacitive Micromachined Ultrasonic Transducers

Further Results on Efficient Implementations of Block Cipher Linear Layers

A Deeper Look at the Energy Consumption of Lightweight Block Ciphers

Three-Input Gates for Logic Synthesis

Sensitivity, Noise and Resolution in a B -Modified Foundry-Made ISFET with Miniaturized Reference Electrode for Wearable Point-of-Care Applications

Consensus Control for Decentralized Deep Learning

Low Noise Clock Generation: Modeling, Analysis and Implementation

Serial Lightweight Implementation Techniques for Block Ciphers

Modeling of Simultaneous Propagation of Multiple Blade‑Like Hydraulic Fractures from a Horizontal Well

An optimized self-sensing piezoelectric cantilever for micro-robotic applications

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Fluorescence lifetime imaging with a single-photon SPAD array using long overlapping gates: an experimental and theoretical study

Computationally Efficient Multiple-Independent-Gate Device Model

Compact Circuits for Combined AES Encryption/Decryption

Scaling-up ESOP Synthesis for Quantum Compilation

A Magnet-Based Timing System to Detect Gate Crossings in Alpine Ski Racing

Idealized digital models for conical reed instruments, with focus on the internal pressure waveform

Bi-directional AC electrothermal micropump for on-chip biological applications