FACETs: Fast and Efficient Compilation for Control–Dataflow Mapping on CGRAs

Reconfigurable computing bridges the gap between the flexibility of general-purpose processors and the efficiency of applicationspecific hardware. Among reconfigurable architectures, Coarse-Grained Reconfigurable Arrays (CGRAs) are particularly promising because they offer high efficiency and low configuration overhead, while maintaining programmability at the operation level. However, mapping high-level applications onto CGRAs remains challenging, as most state-of-the-art approaches either have a limited compilation scope or incur a very high compilation time. To address this challenge, we propose a compilation framework that supports generic control-dataflow graphs by scheduling dataflow graphs under explicit control-flow constraints. The framework adopts a flexible approach that comprises a fast heuristic mapping strategy for non-critical code regions, while enabling aggressive optimizations for performance-critical regions. Experimental results show up to 10× faster compilation for applications with complex control-dataflow graph structures, while achieving comparable or better runtime performance relative to existing approaches.