Publication

Self-Calibrating Networks-On-Chip

Paolo Ienne, Patrick Thiran, Frédéric Worm
2005
Conference Papers

Abstract

Networks-on-chip provide an elegant framework to efficiently reuse predesigned cores. However, reuse of cores is jeopardized by new deep sub-micron noise effects that challenge the reliability of CMOS technology. Moreover, noise margins are further reduced as supply voltages scale down. We advocate that self-calibrating techniques will be needed to maintain an acceptable design trade-off between energy, performance, and reliability. As a result, self-calibrating techniques have to be integrated within networks-on-chip. This paper presents a self-calibrating link and discusses qualitatively the problem of controlling adaptively its voltage and frequency.

Official source

https://infoscience.epfl.ch/entities/publication/324fda38-f3f7-4794-bd74-e367bdc0ec30

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Paolo Ienne, Patrick Thiran, Frédéric Worm
2005
Conference Papers

Abstract

Official source

https://infoscience.epfl.ch/entities/publication/324fda38-f3f7-4794-bd74-e367bdc0ec30

About this result

Related concepts (32)

System on a chip

A system on a chip or system-on-chip (SoC ,ˈɛsoʊsiː; pl. SoCs ,ˈɛsoʊsiːz) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include on-chip central processing unit (CPU), memory interfaces, input/output devices, input/output interfaces, and secondary storage interfaces, often alongside other components such as radio modems and a graphics processing unit (GPU) – all on a single substrate or microchip.

Network on a chip

A network on a chip or network-on-chip (NoC ˌɛnˌoʊˈsiː or nɒk ) is a network-based communications subsystem on an integrated circuit ("microchip"), most typically between modules in a system on a chip (SoC). The modules on the IC are typically semiconductor IP cores schematizing various functions of the computer system, and are designed to be modular in the sense of network science. The network on chip is a router-based packet switching network between SoC modules.

CMOS

Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", siːmɑːs, -ɒs) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS), and other digital logic circuits.

Related publications (1)

Self-Calibrating Networks-On-Chip

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