An Open-Hardware Coarse-Grained Reconfigurable Array for Edge Computing

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Efficient Multi-Word Compare and Swap

Atomic lock-free multi-word compare-and-swap (MCAS) is a powerful tool for designing concurrent algorithms. Yet, its widespread usage has been limited because lock-free implementations of MCAS make heavy use of expensive compare-and-swap (CAS) instructions ...

Schloss Dagstuhl, Leibniz-Zentrum2020

i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing

David Atienza Alonso, Soumya Subhra Basu, Giovanni Ansaloni, Loris Gérard Duch, Miguel Peon Quiros

Smart edge sensors for bio-signal monitoring must support complex signal processing routines within an extremely small energy envelope. Coarse-Grained Reconfigurable Arrays (CGRAs) are good candidates for tackling these conflicting objectives because, than ...

2019

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Paolo Ienne, Sahand Kashani, Andrea Guerrieri

Due to increased embedded processing requirements, modern SoCs are becoming heterogeneous computing platforms by combining traditional processing units with custom reconfigurable hardware accelerators (HAs) on an FPGA fabric. However, efficiently managing ...

2019

Improving Main-memory Database System Performance through Cooperative Multitasking

Georgios Psaropoulos

Database systems access memory either sequentially or randomly. Contrary to sequential access and despite the extensive efforts of computer architects, compiler writers, and system builders, random access to data larger than the processor cache has been s ...

EPFL2019

Asynchronous Branch-Paralle Simulation of Detailed Neuron Models

Felix Schürmann, Michael Lee Hines

Simulations of electrical activity of networks of morphologically detailed neuron models allow for a better understanding of the brain. State-of-the-art simulations describe the dynamics of ionic currents and biochemical processes within branching topologi ...

2019

Fully-Asynchronous Cache-Efficient Simulation of Detailed Neural Networks

Felix Schürmann, Michael Lee Hines

Modern asynchronous runtime systems allow the re-thinking of large-scale scientific applications. With the example of a simulator of morphologically detailed neural networks, we show how detaching from the commonly used bulk-synchronous parallel (BSP) exec ...

SPRINGER INTERNATIONAL PUBLISHING AG2019

Reconciling Being in-Control vs. Being Helped for the Execution of Complex Movements in VR

Ronan Boulic, Bruno Herbelin, Thibault Serge Mario Porssut

Performing motor tasks in virtual environments is best achieved with motion capture and animation of a 3D character that participants control in real time and perceive as being their avatar in the virtual environment. A strong Sense of Embodiment (SoE) for ...

IEEE2019

FPGA-Assisted Deterministic Routing for FPGAs

Mirjana Stojilovic, Dario Korolija

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

2019

BLADE: A BitLine Accelerator for Devices on the Edge

David Atienza Alonso, William Andrew Simon, Marina Zapater Sancho, Yasir Mahmood Qureshi, Alexandre Sébastien Julien Levisse

The increasing ubiquity of edge devices in the consumer market, along with their ever more computationally expensive workloads, necessitate corresponding increases in computing power to support such workloads. In-memory computing is attractive in edge devi ...

2019

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Jonathan Emmanuel D Narinx

The capability to process high-resolution videos in real-time is becoming more important in a wide variety of applications such as autonomous vehicles, virtual reality or intelligent surveillance systems. The high-accuracy and complex video processing algo ...

EPFL2019

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