Layout and Architecture Issues in Hall based CMOS microsystems

The Hall cells intended for industrial applications are mainly produced in silicon integrated circuit technology. Recently, the increased use of other technologies, such as GaAs, InAs and InSb, have been reported. However, a single chip solution comprising the Hall cell and the accompanying electronics has only been realized in silicon technology. A poor mobility of the silicon compare to others III-V high mobility materials makes the sensitivity of a Hall device integrated in a traditional CMOS process low and therefore offset susceptible. Typical offset level of a Hall plate device is in the range of 10 mT, or 500 uV if converted with a typical voltage related sensitivity of 0.05 V/VT and a bias voltage of 1 V. The most efficient method to suppress the offset of the Hall device itself is the spinning current technique. Its efficiency depends on the Hall device bias conditions and the suppression factor is in the range of 50 to 500. It means that the front-end electronics has to treat the signals in the sub-micro volt range. Usually, in publications related to the offset suppression in Hall magnetic sensors, this problem is treated either at the device physics level, as a problem of the Hall device alone, without taking into account limitations of the associated electronic circuits, or as a problem of the sensor electronic circuit with a Hall device represented merely by a very primitive and, therefore, non-adequate model. This distinction prevents a complete analysis of the offset problem and as a consequence the origin of offset in Hall based magnetic systems remains obscure. Our contribution deals with the root cause of an incomplete offset cancellation in a real Hall based microsystem. We demonstrated that the major source of offset and offset drift is the signal treatment electronics. In order to identify the different offset sources in the system and quantify their contributions to the overall offset behaviour, we realized for this purpose a Hall microsystem test chip in 0.35 um CMOS standard process. Based on the results we established the design and layout methodologies, to find out a good trade-off between offset reduction, bandwidth, and current consumption for a given system architecture.