AIPS: AI-Based Power Simulation for Pre-Silicon Side-Channel Security Evaluation

Power side-channel analysis (SCA) attacks pose a significant threat to the security of integrated circuits, making pre-silicon evaluation essential for vulnerability identification. Existing approaches face a fundamental trade-off: commercial electronic design automation (EDA) tools can generate accurate nanosecond-resolution transient power traces, but become prohibitively slow as design size and trace length increase; in contrast, recent artificial intelligence (AI) methods largely target average-power estimation and overlook fine-grained transients critical to SCA. To address this gap, we propose AIPS, an AI-based gate-level power simulation framework that uses a diffusion model to synthesize transient power traces conditioned on switching activity and technology-library features. AIPS is trained on power traces generated by Synopsys PrimeTime PX (PTPX) and evaluated on five representative targets (AES, Kyber, two masked AES variants, and a RISC-V core) using waveform-similarity metrics and first- and higher-order SCA. Results show that AIPS matches PTPX closely under waveform metrics and reproduces the same evaluation outcomes as PTPX under the tested attack settings, while delivering 4.14x–42.44x speedup over PTPX when scaling to 1M traces. In inference-only mode, AIPS achieves up to 10kx speedup. AIPS maintains accuracy with small training sets (about 1k traces or less), and scales favorably with increasing trace length, enabling large-scale pre-silicon side-channel security evaluation.