Publications related to GMS: Generic Memristive Structure for Non-Volatile FPGAs

Related publications (35)

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Time-resolved non-line-of-sight (NLOS) imaging based on single-photon avalanche diode (SPAD) detectors have demonstrated impressive results in recent years. To acquire adequate number of indirect photons from a hidden scene in the presence of overwhelming ...

Ieee-Inst Electrical Electronics Engineers Inc2024

EdgeAI-Aware Design of In-Memory Computing Architectures

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Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

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In the past decades, a significant increase of the transistor density on a chip has led to exponential growth in computational power driven by Moore's law. To overcome the bottleneck of traditional von-Neumann architecture in computational efficiency, effo ...

EPFL2024

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Computer systems rely heavily on abstraction to manage the exponential growth of complexity across hardware and software. Due to practical considerations of compatibility between components of these complex systems across generations, developers have favou ...

EPFL2024

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MDPI2024

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SPIE2024

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The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

2024

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Machine learning and data processing algorithms have been thriving in finding ways of processing and classifying information by exploiting the hidden trends of large datasets. Although these emerging computational methods have become successful in today's ...

EPFL2023

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2023

How to Achieve Large-Area Ultra-Fast Operation of MoS 2 Monolayer Flash Memories?

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Memory devices have returned to the spotlight due to increasing interest in using in-memory computing architectures to make data-driven algorithms more energy-efficient. One of the main advantages of this architecture is the efficient performance of vector ...

2023

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Ognjen Glamocanin

The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...

EPFL2023

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Francesco Regazzoni, Mirjana Stojilovic, Ognjen Glamocanin, Dina Gamaleldin Ahmed Shawky Mahmoud

Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

Springer, Cham2023

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Accessing input data is a critical operation in data analytics: i) slow data access significantly degrades performance, and ii) storing everything in the fastest medium, i.e., memory, incurs high operational and hardware costs. Further, while GPUs offer in ...

2023

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

Chaosity: Understanding Contemporary NUMA-architectures

Andreea Nica, Anastasia Ailamaki, Viktor Sanca, Syed Mohammad Aunn Raza, Hamish Mcniece Hill Nicholson

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

2023

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Mirjana Stojilovic, Stefan Nikolic, Shashwat Shrivastava

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

IEEE2023

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

David Atienza Alonso, Miguel Peon Quiros, Benoît Walter Denkinger

Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The lat ...

2023

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Marco Antonio Rios

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

2023

Engram cell connectivity as a mechanism for information encoding and memory function

Maurizio Ferdinando Pezzoli

Information derived from experiences is incorporated into the brain as changes to ensembles of cells, termed engram cells, which allow memory storage and recall. The mechanism by which those changes hold specific information is unclear. Here, we test the h ...

Cell Press2023

Rebooting Virtual Memory with Midgard

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Virtual Memory (VM) is a critical programming abstraction that is widely used in various modern computing platforms. With the rise of datacenter computing and birth of planet-scale online services, the semantic and capacity requirements from memory have ev ...

EPFL2023