The global transition toward electrification requires highly efficient and compact power electronic converters. Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) offer a promising alternative to silicon power devices. Thanks to their high electron mobility and low ON-resistance, GaN HEMTs enable efficient operation at high switching frequencies, significantly increasing power density.
Despite these benefits, the widespread adoption of GaN technologies, primarily p-GaN gate HEMTs for normally-off operations, is hindered by dynamic performance limitations. Under high-voltage switching, charge trapping within the device causes dynamic ON-resistance (RON) degradation, output capacitance (CO) hysteresis, and threshold voltage (Vth) instability. In addition, GaN HEMTs lack an intrinsic body diode, which results in poor reverse conduction performance and high dead-time losses. Overcoming these limitations requires careful in-circuit characterization to understand their physical root causes before proposing device-level solutions.
This thesis addresses these challenges by bridging realistic circuit-level evaluation with structural device engineering. The first part focuses on in-circuit characterization under steady-state and high-frequency operation to identify mechanisms driving dynamic degradation. By evaluating devices under steady-state switching, we distinguished the trapping mechanisms responsible for dynamic RON in different GaN technologies, extracting their distinct voltage- and temperature-dependent time constants. Furthermore, gate-side and drain-side hole injection was identified as an effective way to mitigate dynamic RON degradation under various switching conditions. We also investigated CO hysteresis, a dominant source of energy loss under MHz soft-switching operations. We proposed a Resonant Sawyer-Tower (RST) method to accurately measure these losses in the sub-µJ range at realistic frequencies, enabling precise evaluation of CO hysteresis and providing a direct approach to compare different epitaxial buffer designs. In addition, we examined dynamic gate instability, showing that Schottky-type p-GaN gates suffer from a positive Vth shift, while Ohmic-type gates exhibit a negative shift.
The second part leverages these insights to propose novel device-level architectures. To address deep-level charge trapping responsible for high-voltage degradation, we proposed a Hole-Enhanced Active Layer (HEAL) structure. This architecture actively manages charge distribution by facilitating hole injection during the ON-state and controlled hole leakage during the OFF-state. The HEAL device demonstrated robust operation, showing less than 20% degradation under a 2000 V OFF-state bias with a floating substrate. Next, to solve the reverse conduction problem and improve switching efficiency, we proposed a double-channel integration scheme of HEMT and Schottky barrier diode (SBD) with a unified tri-gate design. The integrated device ach
