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A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

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A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

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Design Trade-offs of Second Harmonic Minimization in Solid-State Transformers

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Sub-mm3 dimensional scaling of fully-integrated additively-fabricated microsupercapacitors for embedded energy storage applications

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Chaosity: Understanding Contemporary NUMA-architectures

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

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Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Front-End Circuits for Radiation-Hard Monolithic CMOS Sensors targeting High-Energy Physics Applications

Associativity-agnostic in-cache computing memory architecture optimized for multiplication

Enablers for Overcurrent Capability of Silicon-Carbide-Based Power Converters: An Overview

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