STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

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STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

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Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

EdgeAI-Aware Design of In-Memory Computing Architectures

Imaging sensor device using an array of single-photon avalanche diode photodetectors

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Rebooting Virtual Memory with Midgard

HPCache: memory-efficient OLAP through proportional caching revisited

Imprecise Store Exceptions

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

uKharon: A Membership Service for Microsecond Applications

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Fast correlation function calculator A high-performance pair-counting toolkit

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Green Cryptography and Other Optimisations

Caching and Neutrality

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Cooperative Concurrency Control for Write-Intensive Key-Value Workloads

MOD2IR: High-Performance Code Generation for a Biophysically Detailed Neuronal Simulation DSL

SecureCells: A Secure Compartmentalized Architecture

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers