SPADE: Tuning scale-out OLTP on modern RDMA clusters

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Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

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SPADE: Tuning scale-out OLTP on modern RDMA clusters

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Highly Parallel RTL Simulation

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Reliable Microsecond-Scale Distributed Computing

Chaosity: Understanding Contemporary NUMA-architectures

Intelligent RF System for Ultra Low Power Spectrum Sensing with Machine Learning

Artificial Neural Network Training on an Optical Processor via Direct Feedback Alignment

Post-Moore's Law Fusion: High-Bandwidth Memory, Accelerators, and Native Half-Precision Processing for CPU-Local Analytics

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Green Cryptography and Other Optimisations

Overflow-free compute memories for edge AI acceleration

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

Efficient Analytical Query Processing on CPU-GPU Hardware Platforms

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

From C/C plus plus Code to High-Performance Dataflow Circuits

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis