Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability and hardware-level parallelism. While FPGAs are typically used by one tenant at a time, multitenant schemes supporting spatial sharing of c ...

Computer systems rely heavily on abstraction to manage the exponential growth of complexity across hardware and software. Due to practical considerations of compatibility between components of these complex systems across generations, developers have favou ...

Computing servers have played a key role in developing and processing emerging compute-intensive applications in recent years. Consolidating multiple virtual machines (VMs) inside one server to run various applications introduces severe competence for limi ...

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the use ...

In this paper, the design and experimental validation of a prototype phasor measurement unit (PMU) that simultaneously meets the P and M class requirements of the IEC/IEEE Std 60255-118-1-2018 are presented. The device is based on a synchrophasor estimatio ...

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

The TCV tokamak is powered by a flywheel generator to supply the magnetic coils and the auxiliary heating systems. The generator has just undergone its fourth major overhaul to make it ready for the next ten years, after more than thirty years of almost tr ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

Virtual Memory (VM) is a critical programming abstraction that is widely used in various modern computing platforms. With the rise of datacenter computing and birth of planet-scale online services, the semantic and capacity requirements from memory have ev ...

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

A force-feedback surface that creates and modulates distinctive profile and stiffnessto interact with a user in contact thereto, the surface being functionally independentto be used as a single module but can be customized to extend the application indiver ...

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

ML-based edge devices may face memory and computational errors that affect applications' reliability and performance. These errors can be the result of particular working conditions (e.g., radiation areas in physical experiments or avionics) or could be th ...

Accessing input data is a critical operation in data analytics: i) slow data access significantly degrades performance, and ii) storing everything in the fastest medium, i.e., memory, incurs high operational and hardware costs. Further, while GPUs offer in ...

The crowdedness of the RF spectrum constitutes problems in communication, however it also accommodates large amount of useful information. This information can be used to determine existing signals and operating contexts. However, spectrum condition varies ...

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Chat with Graph Search

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

Secure Interface Design Leveraging Hardware/Software Support

CloudProphet: A Machine Learning-Based Performance Prediction for Public Clouds

Highly Parallel RTL Simulation

EdgeAI-Aware Design of In-Memory Computing Architectures

Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

Implementation and validation of a dual P- and M- class compliant PMU prototype based on the delayed in-quadrature interpolated DFT

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Maintenance and optimization of the TCV power supply

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Rebooting Virtual Memory with Midgard

Chaosity: Understanding Contemporary NUMA-architectures

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Device and system as human interactive surface

A Visionary Look at the Security of Reconfigurable Cloud Computing

Hardware-Software co-design Methodologies for Edge AI Optimization

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Intelligent RF System for Ultra Low Power Spectrum Sensing with Machine Learning

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference