Distributed Computing with Modern Shared Memory

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Compute memories are memory arrays augmented with dedicated logic to support arithmetic. They support the efficient execution of data-centric computing patterns, such as those characterizing Artificial Intelligence (AI) algorithms. These architectures can ...

Modern data management systems aim to provide both cutting-edge functionality and hardware efficiency. With the advent of AI-driven data processing and the post-Moore Law era, traditional memory-bound scale-up data management operations face scalability ch ...

The landscape of computing is changing, thanks to the advent of modern networking equipment that allows machines to exchange information in as little as one microsecond. Such advancement has enabled microsecond-scale distributed computing, where entire dis ...

Information derived from experiences is incorporated into the brain as changes to ensembles of cells, termed engram cells, which allow memory storage and recall. The mechanism by which those changes hold specific information is unclear. Here, we test the h ...

Most modern in-memory online transaction processing (OLTP) engines rely on multi-version concurrency control (MVCC) to provide data consistency guarantees in the presence of conflicting data accesses. MVCC improves concurrency by generating a new version o ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

State-of-the-art Artificial Intelligence (AI) algorithms, such as graph neural networks and recommendation systems, require floating-point computation of very large matrix multiplications over sparse data. Their execution in resource-constrained scenarios, ...

This short essay illustrates the role of the business archive in the transmission and maintenance of contemporary industrial culture, with a focus on the company town of Dalmine. In the context of Dalmine, the business archive managed by the Fondazione Dal ...

Precise exceptions are a cornerstone of modern computing as they provide the abstraction of sequential instruction execution to programmers while accommodating microarchitectural optimizations. However, increasing compute capabilities in deep memory hierar ...

A memory engram is thought to be the physical substrate of the memory trace within the brain, which is generally depicted as a neuronal ensemble activated by learning to fire together during encoding and retrieval. It has been postulated that engram cell e ...

This thesis demonstrates that it is feasible for systems code to expose a latency interface that describes its latency and related side effects for all inputs, just like the code's semantic interface describes its functionality and related side effects. S ...

Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The lat ...

Distributed Computing with Modern Shared Memory

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Overflow-free compute memories for edge AI acceleration

Post-Moore's Law Fusion: High-Bandwidth Memory, Accelerators, and Native Half-Precision Processing for CPU-Local Analytics

Reliable Microsecond-Scale Distributed Computing

Engram cell connectivity as a mechanism for information encoding and memory function

One-shot Garbage Collection for In-memory OLTP through Temporality-aware Version Storage

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication

When the industry built the city: business archives, memory and community in a contemporary company town

Imprecise Store Exceptions

Tissue clearing applications in memory engram research

Latency Interfaces for Systems Code

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems